Abstract: The memory controller forms temporary virtual blocks each composed of a plurality of physical blocks, whose physical addresses are the same value, each of which is included in each of flash memories, extracts temporary virtual block to which at least one defective block belongs from the temporary virtual blocks, generates a second temporary virtual block to which a defective block does not belong by replacing a defective block belonging to one temporary virtual block with a normal block belonging to another temporary virtual block among temporary virtual blocks extracted, and allocates temporary virtual blocks not extracted and second temporary virtual blocks generated to available virtual blocks.

Abstract: In a case where at least one of physical blocks composing the virtual block becomes a defective block, use of the virtual block to which the defective block belongs is forbidden and the virtual block of which use is forbidden is managed as a defective virtual block. Replacing the defective block with a normal block is performed among the defective virtual blocks so as to generate the virtual block to which the defective block does not belong. Then use of the virtual block generated is allowed.

Abstract: There is disclosed a controller included in a flash memory system attachable to a memory interface of a host system. The controller performs a process for minimizing the maximum number of defective blocks to be classified into each zone, by using a plurality of replacement tables or a plurality of functions. Specifically, a dispersion process unit included in the controller associates virtual block addresses VBA with physical block addresses PBA so as to minimize the maximum number of defective blocks to be classified into each zone. The flash memory system may have a plurality of replacement tables describing correspondence between virtual block addresses VBA and physical block addresses PBA. Or, in the flash memory system, plural kinds of functions for setting correspondence between virtual block addresses VBA and physical block addresses PBA may be defined by the controller.

Abstract: The memory controller forms temporary virtual blocks each composed of a plurality of physical blocks, whose physical addresses are the same value, each of which is included in each of flash memories, extracts temporary virtual block to which at least one defective block belongs from the temporary virtual blocks, generates a second temporary virtual block to which a defective block does not belong by replacing a defective block belonging to one temporary virtual block with a normal block belonging to another temporary virtual block among temporary virtual blocks extracted, and allocates temporary virtual blocks not extracted and second temporary virtual blocks generated to available virtual blocks.

Abstract: In a case where at least one of physical blocks composing the virtual block becomes a defective block, use of the virtual block to which the defective block belongs is forbidden and the virtual block of which use is forbidden is managed as a defective virtual block. Replacing the defective block with a normal block is performed among the defective virtual blocks so as to generate the virtual block to which the defective block does not belong. Then use of the virtual block generated is allowed.

Abstract: A memory controller includes decision means responsive to a request to write user data issued by a host computer for determining whether progressive data writing for writing user data to a target page designated by a host address is possible, and write means responsive to an affirmative determination by the decision means for writing user data to the target page without performing an inter-block data transfer. Thus, a series of data write operations for completing data writing can be performed at high speed because the frequency of inter-block data transfers is low.

Abstract: There is disclosed a controller included in a flash memory system attachable to a memory interface of a host system. The controller performs a process for minimizing the maximum number of defective blocks to be classified into each zone, by using a plurality of replacement tables or a plurality of functions. Specifically, a dispersion process unit included in the controller associates virtual block addresses VBA with physical block addresses PBA so as to minimize the maximum number of defective blocks to be classified into each zone. The flash memory system may have a plurality of replacement tables describing correspondence between virtual block addresses VBA and physical block addresses PBA. Or, in the flash memory system, plural kinds of functions for setting correspondence between virtual block addresses VBA and physical block addresses PBA may be defined by the controller.

Abstract: There is disclosed a controller included in a flash memory system attachable to a memory interface of a host system. The controller performs a process for minimizing the maximum number of defective blocks to be classified into each zone, by using a plurality of replacement tables or a plurality of functions. Specifically, a dispersion process unit included in the controller associates virtual block addresses VBA with physical block addresses PBA so as to minimize the maximum number of defective blocks to be classified into each zone. The flash memory system may have a plurality of replacement tables describing correspondence between virtual block addresses VBA and physical block addresses PBA. Or, in the flash memory system, plural kinds of functions for setting correspondence between virtual block addresses VBA and physical block addresses PBA may be defined by the controller.

Abstract: An object of the present invention is to provide a memory controller that can perform a series of data write operations so as to complete the data writing at high speed. A memory controller includes means for dividing the physical blocks into a plurality of groups, means for forming a plurality of virtual blocks by virtually combining a plurality of physical blocks each of which belongs to a different group, and means for assigning adjacent host addresses to different physical blocks belonging to the same virtual block. Thus, when a host computer issues a request to access the plurality of successive host addresses, the physical blocks to be accessed are different physical blocks. Since the physical blocks to be accessed can therefore operate independently, a series of operations can be performed in parallel.

Abstract: There is disclosed a controller included in a flash memory system attachable to a memory interface of a host system. The controller performs a process for minimizing the maximum number of defective blocks to be classified into each zone, by using a plurality of replacement tables or a plurality of functions. Specifically, a dispersion process unit included in the controller associates virtual block addresses VBA with physical block addresses PBA so as to minimize the maximum number of defective blocks to be classified into each zone. The flash memory system may have a plurality of replacement tables describing correspondence between virtual block addresses VBA and physical block addresses PBA. Or, in the flash memory system, plural kinds of functions for setting correspondence between virtual block addresses VBA and physical block addresses PBA may be defined by the controller.

Abstract: An object of the present invention is to provide a memory controller that can perform a series of data write operations so as to complete the data writing at high speed.

Abstract: A memory controller includes decision means responsive to a request to write user data issued by a host computer for determining whether progressive data writing for writing user data to a target page designated by a host address is possible, and write means responsive to an affirmative determination by the decision means for writing user data to the target page without performing an inter-block data transfer. Thus, a series of data write operations for completing data writing can be performed at high speed because the frequency of inter-block data transfers is low.