Patents by Inventor Kenzo Kuwabara

Kenzo Kuwabara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit
    Patent number: 7945801
    Abstract: A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: May 17, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Shigezumi Matsui, Takashi Sato, Kazuyuki Sakata, Tsuyoshi Yaguchi, Kenzo Kuwabara, Atsushi Nakamura, Motoo Suwa, Ryoichi Sano, Hisashi Shiota
  • SEMICONDUCTOR INTEGRATED CIRCUIT
    Publication number: 20080276112
    Abstract: A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.
    Type: Application
    Filed: July 9, 2008
    Publication date: November 6, 2008
    Inventors: SHIGEZUMI MATSUI, Takashi Sato, Kazuyuki Sakata, Tsuyoshi Yaguchi, Kenzo Kuwabara, Atsushi Nakamura, Motoo Suwa, Ryoichi Sano, Hisashi Shiota
  • Semiconductor integrated circuit
    Patent number: 7412616
    Abstract: A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: August 12, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Shigezumi Matsui, Takashi Sato, Kazuyuki Sakata, Tsuyoshi Yaguchi, Kenzo Kuwabara, Atsushi Nakamura, Motoo Suwa, Ryoichi Sano, Hisashi Shiota
  • Semiconductor integrated circuit
    Publication number: 20050047192
    Abstract: A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.
    Type: Application
    Filed: July 21, 2004
    Publication date: March 3, 2005
    Inventors: Shigezumi Matsui, Takashi Sato, Kazuyuki Sakata, Tsuyoshi Yaguchi, Kenzo Kuwabara, Atsushi Nakamura, Motoo Suwa, Ryoichi Sano, Hisashi Shiota