Abstract: An intellectual property (IP) recommending method and an IP recommending system are provided. In the method, a plurality of IP portfolios respectively designated for a plurality of product designs are retrieved and usage data of a plurality of IPs included in each of the plurality of IP portfolios are extracted. A machine learning (ML) model is trained by using a portion of the retrieved IP portfolios and the extracted usage data. In response to receiving at least one criterion for a desired product design from a user, a plurality of IPs adapted for the desired product design are predicted based on the ML model and recommended for the user.

Abstract: An intellectual property (IP) recommending method and an IP recommending system are provided. In the method, a plurality of IP portfolios respectively designated for a plurality of product designs are retrieved and usage data of a plurality of IPs included in each of the plurality of IP portfolios are extracted. A machine learning (ML) model is trained by using a portion of the retrieved IP portfolios and the extracted usage data. In response to receiving at least one criterion for a desired product design from a user, a plurality of IPs adapted for the desired product design are predicted based on the ML model and recommended for the user.

Abstract: A method of checking an integrated circuit design database includes providing the integrated circuit design stored in a storage media; providing application rules; and providing an instance abstract of instances of libraries and IP(s). Instance-level information is extracted from the integrated circuit design database. An application-rule check is performed against the instance-level information using the information provided in an abstract file.

Abstract: A semiconductor device including a plurality of input/output cells and having a first bond pad and at least one second bond pad coupled to each input/output cell. The first bond pads comprise a first pattern, and the at least second bond pads comprise at least one second pattern, wherein the at least one second pattern is different from or the same as the first pattern. Either the first bond pads, the at least second bond pads, or both, may be used to electrically couple the input/output cells of the semiconductor device to leads of an integrated circuit package or other circuit component.

Abstract: An integrated circuit (IC) including a core area containing active devices and at least one input/output (I/O) cell configured to transfer signals into and out of the core area. The at least one I/O cell includes a gate orientation, a pre-driver module, and at least one post-driver module. The pre-driver module and the at least one post-driver module are offset from each other by an angle between zero and ninety degrees with respect to the gate orientation. The gate orientation for every one of the at least one I/O cell is substantially the same.

Abstract: An integrated circuit (IC) including a core area containing active devices and at least one input/output (I/O) cell configured to transfer signals into and out of the core area. The at least one I/O cell includes a gate orientation, a pre-driver module, and at least one post-driver module. The pre-driver module and the at least one post-driver module are offset from each other by an angle between zero and ninety degrees with respect to the gate orientation. The gate orientation for every one of the at least one I/O cell is substantially the same.

Abstract: A method of checking an integrated circuit design database includes providing the integrated circuit design stored in a storage media; providing application rules; and providing an instance abstract of instances of libraries and IP(s). Instance-level information is extracted from the integrated circuit design database. An application-rule check is performed against the instance-level information using the information provided in an abstract file.

Abstract: A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a switching device coupled between a drain of one of the pair of PMOS transistors and a drain of the NMOS transistor, wherein the pair of PMOS transistors are high voltage transistors and the switching device is off when the VCCL is below a predetermined voltage level, and the switching device is on when the VCCL is above the predetermined voltage level.

Abstract: A method for program routing a circuit with at least a first and second voltages in a single layer is disclosed, which comprises defining a first and second layer types corresponding to the first and second voltages, respectively, specifying at least one first attribute for the first layer type and at least one second attribute for the second layer type, specifying at least one first net with a first voltage and at least one second net with a second voltage, reading the voltage information associated with the first net and the second net by a computer program, routing at least one first polygon for the first net onto the first layer type with the first attribute by the computer program, and routing at least one second polygon for the second net onto the second layer type with the second attribute by the same computer program.

Abstract: An on-chip logic cell timing characterization circuit is provided. Also provided are a method of conducting setup/hold characterization on a sequential cell and a method of characterizing propagation delay on a logic cell. A sequential cell on which setup/hold time is to be characterized is formed in duplicate with one close to the other. A first clock signal is sampled at a transition of a second clock signal on one sequential cell, and a setup time is determined by a state transition in the output signal of the first sequential. The second clock signal is sampled at a transition of the first clock signal on the other sequential cell, and a hold time is determined by a state transition in the output signal of the second sequential cell.

Abstract: A semiconductor device including a plurality of input/output cells and having a first bond pad and at least one second bond pad coupled to each input/output cell. The first bond pads comprise a first pattern, and the at least second bond pads comprise at least one second pattern, wherein the at least one second pattern is different from or the same as the first pattern. Either the first bond pads, the at least second bond pads, or both, may be used to electrically couple the input/output cells of the semiconductor device to leads of an integrated circuit package or other circuit component.

Abstract: An on-chip logic cell timing characterization circuit is provided. Also provided are a method of conducting setup/hold characterization on a sequential cell and a method of characterizing propagation delay on a logic cell. A sequential cell on which setup/hold time is to be characterized is formed in duplicate with one close to the other. A first clock signal is sampled at a transition of a second clock signal on one sequential cell, and a setup time is determined by a state transition in the output signal of the first sequential. The second clock signal is sampled at a transition of the first clock signal on the other sequential cell, and a hold time is determined by a state transition in the output signal of the second sequential cell.

Abstract: A semiconductor device including a plurality of input/output cells and having a first bond pad and at least one second bond pad coupled to each input/output cell. The first bond pads comprise a first pattern, and the at least second bond pads comprise at least one second pattern, wherein the at least one second pattern is different from or the same as the first pattern. Either the first bond pads, the at least second bond pads, or both, may be used to electrically couple the input/output cells of the semiconductor device to leads of an integrated circuit package or other circuit component.

Abstract: A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a switching device coupled between a drain of one of the pair of PMOS transistors and a drain of the NMOS transistor, wherein the pair of PMOS transistors are high voltage transistors and the switching device is off when the VCCL is below a predetermined voltage level, and the switching device is on when the VCCL is above the predetermined voltage level.

Abstract: This invention discloses an integrated circuit (IC) chip which comprises a first, second and third bonding pad connected exclusively to a first, second and third probing pad, respectively, wherein the first bonding pad, the second probing pad and the third bonding pad are substantially aligned linearly with the second probing pad being placed between the first and third bonding pad.

Abstract: An integrated circuit system includes a first device in a first power domain, and a second device coupled to the first device in a second power domain. A circuit module is coupled between the first device and a power supply voltage or between the first device and a complementary power supply voltage in the first power domain for increasing an impedance against an ESD current flowing from the first device to the second device during an ESD event.

Abstract: A microchip includes at least one I/O area surrounding at least one core circuit area. The I/O area further includes a first I/O cell having at least one first post-driver device connected to a first I/O pad; a second I/O cell having at least one second post-driver device connected to a second I/O pad; and an electrostatic discharge (ESD) cluster shared by the first I/O cell and the second I/O cell for protecting the same against ESD current during an ESD event, thereby reducing a total width of the first I/O cell and the second I/O cell.

Abstract: This invention discloses a ballasting resistor for an electrostatic discharge (ESD) device that comprises at least one first active region forming a source/drain of an ESD discharge transistor, at least one resistive element with a serpentine shape formed in a single layer of a semiconductor structure, wherein the resistive element has a first terminal coupled to the first active region and a second terminal coupled to a bonding pad including power supply (Vdd or Vss) pads.

Abstract: I. A method and system is disclosed for generating a desired input/output (I/O) cell based on a basic cell from a library. After identifying a configuration requirement for a desired I/O cell to be used for an integrated circuit design, at least one basic cell is selected, the basic cell having a base component for generating the desired I/O cell to meet the configuration requirement. A connection template is generated having one or more programmable connection points identified thereon, the programmable connection points identifying locations for making connections to one or more feature components of the basic cell. The selected basic cell and the connection template are combined to generate a design file, wherein the design file corresponds to the desired I/O cell with the predetermined feature components of the basic cell integrated with the basic component to satisfy the configuration requirement. The disclosed method reduces the design cycle-time as well as circuit-library maintenance and update effort.

Abstract: A method for program routing a circuit with at least a first and second voltages in a single layer is disclosed, which comprises defining a first and second layer types corresponding to the first and second voltages, respectively, specifying at least one first attribute for the first layer type and at least one second attribute for the second layer type, specifying at least one first net with a first voltage and at least one second net with a second voltage, reading the voltage information associated with the first net and the second net by a computer program, routing at least one first polygon for the first net onto the first layer type with the first attribute by the computer program, and routing at least one second polygon for the second net onto the second layer type with the second attribute by the same computer program.