Patents by Inventor Kesami Hagiwara
Kesami Hagiwara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10642596Abstract: An object of the present invention is to perform a program updating process without reconstructing a program using a pre-update program and an update differential program. An embedded device has a nonvolatile memory having a plurality of planes from/to which data can be read/written independently and an address translator performing address translation by using an address translation table. When an address obtained by decoding an instruction by a CPU is an address corresponding to a change part in a default program, the address translator translates the address to an address in which a differential program is disposed.Type: GrantFiled: February 28, 2017Date of Patent: May 5, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tadaaki Tanimoto, Kesami Hagiwara, Naoyuki Morita
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Publication number: 20170255459Abstract: An object of the present invention is to perform a program updating process without reconstructing a program using a pre-update program and an update differential program. An embedded device has a nonvolatile memory having a plurality of planes from/to which data can be read/written independently and an address translator performing address translation by using an address translation table. When an address obtained by decoding an instruction by a CPU is an address corresponding to a change part in a default program, the address translator translates the address to an address in which a differential program is disposed.Type: ApplicationFiled: February 28, 2017Publication date: September 7, 2017Inventors: Tadaaki TANIMOTO, Kesami HAGIWARA, Naoyuki MORITA
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Patent number: 9367438Abstract: First data to be written which is output from a function module (2) is supplied to a built-in memory (3) and a first buffer memory (11), and second data to be written which is output from the function module (2) is supplied to the built-in memory (3) and a second buffer memory (12). The first and second FIFO memories (13, 14) select and store data items having a predetermined number of outputs from a plurality of first and second output data items which are sequentially output from the first and second buffer memories (11, 12), and do not select other data items. A comparator (15) compares the data items having the predetermined number of outputs which are selected and are output by the first and second FIFO memories (13, 14) with each other.Type: GrantFiled: April 21, 2011Date of Patent: June 14, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiromichi Yamada, Nobuyasu Kanekawa, Teruaki Sakata, Kesami Hagiwara, Yuichi Ishiguro
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Patent number: 9323595Abstract: A microcontroller includes a central processing unit, a PWM signal generation unit which generates a PWM signal according to a generation condition of a PWM signal set by the central processing unit, and a diagnostic unit which inputs the generated PWM signal therein and detects a pulse period and a pulse width, based on the input signal and which determines whether the detected pulse period and pulse width respectively coincide with a pulse period and a pulse width corresponding to the generation condition.Type: GrantFiled: July 21, 2012Date of Patent: April 26, 2016Assignee: Renesas Electronics CorporationInventors: Hiromichi Yamada, Teruaki Sakata, Nobuyasu Kanekawa, Yuichi Ishiguro, Takashi Yasumasu, Kazuyoshi Fukuda, Kesami Hagiwara
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Patent number: 9229830Abstract: To have a problem of occurrence of the same failure in failure detection of a microcontroller. A microcontroller has a CPU and a data access control circuit. The data access control circuit performs two types of accesses: an individual access in which a data access of the CPU is performed for each thread, and a shared access in which a data access of the CPU is performed by executing two threads. The data access control circuit detects a failure of the CPU by making a comparison between the command and the address, respectively, in the shared access generated by executing the two threads.Type: GrantFiled: September 20, 2013Date of Patent: January 5, 2016Assignee: Renesas Electronics CorporationInventors: Hiromichi Yamada, Tsutomu Yamada, Nobuyasu Kanekawa, Kesami Hagiwara, Yuichi Ishiguro, Takashi Yasumasu, Kazuyoshi Fukuda, Yoshiyuki Nakada
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Publication number: 20150234661Abstract: A processor system, includes a first central processing unit (CPU) that executes a redundant instruction set; and a second CPU that executes the redundant instruction set, wherein before the second CPU executes a redundant instruction among the redundant instruction set, the first CPU is able to execute n (n is a predetermined integer number) redundant instructions among the redundant instruction set, and wherein when an exception occurs during execution of the redundant instruction set in the first CPU, the first CPU executes an instruction for the exception as a non-redundant instruction.Type: ApplicationFiled: May 5, 2015Publication date: August 20, 2015Inventors: Hiromichi YAMADA, Nobuyasu KANEKAWA, Tsutomu YAMADA, Kesami HAGIWARA
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Patent number: 9063907Abstract: The present invention provides a semiconductor integrated circuit device realizing improved detection of a failure while suppressing deterioration in performance. In a semiconductor integrated circuit device executing a plurality of threads while switching them synchronously with clocks, registers used for executing the threads are provided for the respective threads. Programs independent of each other and the same program as the threads are executed while being switched. In the case of executing the same program by a plurality of threads, a comparison circuit for comparing results of execution using registers provided in correspondence with the threads is provided.Type: GrantFiled: March 12, 2013Date of Patent: June 23, 2015Assignee: Renesas Electronics CorporationInventors: Hiromichi Yamada, Nobuyasu Kanekawa, Tsutomu Yamada, Kesami Hagiwara
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Publication number: 20150046759Abstract: A micro controller with fault detection function is provided, in which duplex processing by a program is realized without complicating the program. Peripheral circuits are provided with registers and execute processing based on a command. A central processing unit executes twice processing by the same program that accesses the register. A duplex access control circuit is configured with a peripheral bus access unit, a buffer, and a comparator unit. The peripheral bus access unit controls the access to the register by the central processing unit in the first program execution. The buffer stores the access information to the register in the first program execution. The comparator unit compares the access information in the second program execution with the access information stored in the access information storage unit. In the case of disagreement, an error signal is outputted to the central processing unit.Type: ApplicationFiled: August 9, 2014Publication date: February 12, 2015Inventors: HIROMICHI YAMADA, NOBUYASU KANEKAWA, TSUTOMU YAMADA, KESAMI HAGIWARA, YUICHI ISHIGURO, TAKASHI YASUMASU, KAZUYOSHI FUKUDA, YOSHIYUKI NAKADA
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Patent number: 8839029Abstract: A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of CPUs. A plurality of processing systems including CPUs and memories are provided, data output from the CPUs in each of the processing systems is separately compressed and stored by compressors for each of the CPUs, respectively. The compressed storage data is mutually compared by a comparator, and abnormality of processing can be detected when the comparison result indicates a mismatch. Even when the timings by which the same processing results are obtained are different when the plurality of CPUs asynchronously execute the same processing, the processing results of both of them can be easily compared with each other since compression is carried out by the compressors.Type: GrantFiled: April 4, 2013Date of Patent: September 16, 2014Assignee: Renesas Electronics CorporationInventors: Hiromichi Yamada, Kotaro Shimamura, Kesami Hagiwara, Yoshikazu Kiyoshige, Yuichi Ishiguro
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Publication number: 20140082427Abstract: To have a problem of occurrence of the same failure in failure detection of a microcontroller. A microcontroller has a CPU and a data access control circuit. The data access control circuit performs two types of accesses: an individual access in which a data access of the CPU is performed for each thread, and a shared access in which a data access of the CPU is performed by executing two threads. The data access control circuit detects a failure of the CPU by making a comparison between the command and the address, respectively, in the shared access generated by executing the two threads.Type: ApplicationFiled: September 20, 2013Publication date: March 20, 2014Applicant: Renesas Electrics CorporationInventors: Hiromichi Yamada, Tsutomu Yamada, Nobuyasu Kanekawa, Kesami Hagiwara, Yuichi Ishiguro, Takashi Yasumasu, Kazuyoshi Fukuda, Yoshiyuki Nakada
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Publication number: 20140032860Abstract: First data to be written which is output from a function module (2) is supplied to a built-in memory (3) and a first buffer memory (11), and second data to be written which is output from the function module (2) is supplied to the built-in memory (3) and a second buffer memory (12). The first and second FIFO memories (13, 14) select and store data items having a predetermined number of outputs from a plurality of first and second output data items which are sequentially output from the first and second buffer memories (11, 12), and do not select other data items. A comparator (15) compares the data items having the predetermined number of outputs which are selected and are output by the first and second FIFO memories (13, 14) with each other.Type: ApplicationFiled: April 21, 2011Publication date: January 30, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hiromichi Yamada, Nobuyasu Kanekawa, Teruaki Sakata, Kesami Hagiwara, Yuichi Ishiguro
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Publication number: 20130254592Abstract: The present invention provides a semiconductor integrated circuit device realizing improved detection of a failure while suppressing deterioration in performance. In a semiconductor integrated circuit device executing a plurality of threads while switching them synchronously with clocks, registers used for executing the threads are provided for the respective threads. Programs independent of each other and the same program as the threads are executed while being switched. In the case of executing the same program by a plurality of threads, a comparison circuit for comparing results of execution using registers provided in correspondence with the threads is provided.Type: ApplicationFiled: March 12, 2013Publication date: September 26, 2013Applicant: Renesas Electronics CorporationInventors: Hiromichi YAMADA, Nobuyasu Kanekawa, Tsutomu Yamada, Kesami Hagiwara
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Publication number: 20130232383Abstract: A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of CPUs. A plurality of processing systems including CPUs and memories are provided, data output from the CPUs in each of the processing systems is separately compressed and stored by compressors for each of the CPUs, respectively. The compressed storage data is mutually compared by a comparator, and abnormality of processing can be detected when the comparison result indicates a mismatch. Even when the timings by which the same processing results are obtained are different when the plurality of CPUs asynchronously execute the same processing, the processing results of both of them can be easily compared with each other since compression is carried out by the compressors.Type: ApplicationFiled: April 4, 2013Publication date: September 5, 2013Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hiromichi YAMADA, Kotaro SHIMAMURA, Kesami HAGIWARA, Yoshikazu KIYOSHIGE, Yuichi ISHIGURO
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Patent number: 8433955Abstract: A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of CPUs. A plurality of processing systems including CPUs and memories are provided, data output from the CPUs in each of the processing systems is separately compressed and stored by compressors for each of the CPUs, respectively. The compressed storage data is mutually compared by a comparator, and abnormality of processing can be detected when the comparison result indicates a mismatch. Even when the timings by which the same processing results are obtained are different when the plurality of CPUs asynchronously execute the same processing, the processing results of both of them can be easily compared with each other since compression is carried out by the compressors.Type: GrantFiled: November 2, 2009Date of Patent: April 30, 2013Assignee: Renesas Electronics CorporationInventors: Hiromichi Yamada, Kotaro Shimamura, Kesami Hagiwara, Yoshikazu Kiyoshige, Yuichi Ishiguro
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Publication number: 20130020978Abstract: A microcontroller includes a central processing unit, a PWM signal generation unit which generates a PWM signal according to a generation condition of a PWM signal set by the central processing unit, and a diagnostic unit which inputs the generated PWM signal therein and detects a pulse period and a pulse width, based on the input signal and which determines whether the detected pulse period and pulse width respectively coincide with a pulse period and a pulse width corresponding to the generation condition.Type: ApplicationFiled: July 21, 2012Publication date: January 24, 2013Inventors: Hiromichi YAMADA, Teruaki Sakata, Nobuyasu Kanekawa, Yuichi Ishiguro, Takashi Yasumasu, Kazuyoshi Fukuda, Kesami Hagiwara
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Patent number: 8095825Abstract: This method is an error correction method such that, when an error is detected in a CPU with pipeline structure, a content of a register file is restored by a delayed register file which holds an execute completion state of an [Instruction N] correctly executed before this error, and a rollback control that re-executes an instruction from the [Instruction N+1] which is the next instruction of the [Instruction N] is performed. The method collects a parity check result of arbitrary Flip-Flops existing inside the CPU, and detects an error. As a result, the content of the register file is restored into the instruction execute completion state preceding to the instruction range likely to malfunction by the error, and the instruction can be roll backed from the beginning of the instruction range likely having malfunctioned by the error.Type: GrantFiled: January 16, 2007Date of Patent: January 10, 2012Assignee: Renesas Electronics CorporationInventors: Teppei Hirotsu, Hiromichi Yamada, Teruaki Sakata, Kesami Hagiwara
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Patent number: 8082398Abstract: There is a need for providing a data processor capable of easily prefetching data from a wide range. A central processing unit is capable of performing a specified instruction that adds an offset to a value of a register to generate an effective address for data. This register can be assigned an intended value in accordance with execution of an instruction. A buffer maintains part of instruction streams and data streams stored in memory. The buffer includes cache memories for storing the instruction stream and the data stream. From the memory, the buffer prefetches a data stream containing data corresponding to an effective address designated by the specified instruction stored in the cache memory. A data prefetch operation is easy because a data stream is prefetched by finding the specified instruction from the fetched instruction stream. Data can be prefetched from a wider range than the use of a PC-relative load instruction.Type: GrantFiled: March 30, 2009Date of Patent: December 20, 2011Assignee: Renesas Electronics CorporationInventors: Tetsuya Yamada, Naoki Kato, Kesami Hagiwara
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Publication number: 20100131741Abstract: A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of CPUs. A plurality of processing systems including CPUs and memories are provided, data output from the CPUs in each of the processing systems is separately compressed and stored by compressors for each of the CPUs, respectively. The compressed storage data is mutually compared by a comparator, and abnormality of processing can be detected when the comparison result indicates a mismatch. Even when the timings by which the same processing results are obtained are different when the plurality of CPUs asynchronously execute the same processing, the processing results of both of them can be easily compared with each other since compression is carried out by the compressors.Type: ApplicationFiled: November 2, 2009Publication date: May 27, 2010Inventors: Hiromichi YAMADA, Kotaro Shimamura, Kesami Hagiwara, Yoshikazu Kiyoshige, Yuichi Ishiguro
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Publication number: 20090271576Abstract: There is a need for providing a data processor capable of easily prefetching data from a wide range. A central processing unit is capable of performing a specified instruction that adds an offset to a value of a register to generate an effective address for data. This register can be assigned an intended value in accordance with execution of an instruction. A buffer maintains part of instruction streams and data streams stored in memory. The buffer includes cache memories for storing the instruction stream and the data stream. From the memory, the buffer prefetches a data stream containing data corresponding to an effective address designated by the specified instruction stored in the cache memory. A data prefetch operation is easy because a data stream is prefetched by finding the specified instruction from the fetched instruction stream. Data can be prefetched from a wider range than the use of a PC-relative load instruction.Type: ApplicationFiled: March 30, 2009Publication date: October 29, 2009Inventors: Tetsuya Yamada, Naoki Kato, Kesami Hagiwara
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Patent number: 7581054Abstract: In a multiprocessor, one of two local memories can be accessed at a high speed by one of the two processors and also accessed by the other processor. In a multiprocessor, first and second local memories are coupled to first and second processors via first and second local buses. First and second bus bridges are coupled to a system bus and the first and second local buses. First and second bus interface units are coupled to the system bus and the first and second local memories. A high-speed access is made from the first processor to the first local memory via the first local bus. The first local memory is also accessed from the first processor via the first local bus, the first bus bridge, the system bus, and the first and third ports of the second bus interface unit and from the second processor via the second local bus, the second bus bridge, the system bus, and the second and third ports of the first bus interface unit.Type: GrantFiled: July 17, 2007Date of Patent: August 25, 2009Assignee: Renesas Technology Corp.Inventors: Kesami Hagiwara, Takeshi Kataoka, Hisakazu Sato, Shunichi Iwata, Yoshikazu Kiyoshige, Akihiko Tomita