Abstract: A method includes setting an output of each memory cell in an array of memory cells to a same first value, decreasing power to the array of memory cells and then increasing power to the array of memory cells. Memory cells in the array of memory cells with outputs that switched to a second value different from the first value are then identified in response to decreasing and then increasing the power. A set of memory cells is then selected from the identified memory cells to use in hardware security.

Abstract: A method includes receiving a first polynomial and a second polynomial, both of order n?1 and forming d polynomial segments from both the first polynomial and the second polynomial such that each polynomial segment is of order (n/d)?1. The polynomial segments of the first polynomial and the d polynomial segments of the second polynomial are used to form segment products. Each segment product is divided into a first polynomial substructure of order n/d and a second polynomial substructure of order (n/d)?1. A first polynomial substructure containing the first n/d coefficients of a product of the first polynomial and the second polynomial is summed with a second polynomial substructure to form a sum substructure. The sum substructure is used multiple times to determine coefficients of a polynomial representing the modulo xn+1 of the product of the first polynomial and the second polynomial.

Abstract: A modular polynomial multiplier includes a plurality of processing elements. Each includes a multiplication unit, an addition unit and a delay unit. The addition unit has an input connected to the output of the multiplication unit. The delay unit is connected to the output of the addition unit delays values by one clock cycle. The first input of the multiplication unit of each processing element carries a respective coefficient of a first polynomial and the second input of the multiplication unit of each processing element is connected to one of an input line carrying a sequence of coefficients of a second polynomial having n coefficients and a delay line carrying the sequence of coefficients of the second polynomial delayed by n clock cycles and negated.

Abstract: An apparatus includes a first feed-forward PUF, a second feed-forward PUF and an exclusive-or circuit configured to perform an exclusive-or operation of an output of the first feed-forward PUF and an output of the second feed-forward PUF.

Abstract: A method includes setting an output of each memory cell in an array of memory cells to a same first value, decreasing power to the array of memory cells and then increasing power to the array of memory cells. Memory cells in the array of memory cells with outputs that switched to a second value different from the first value are then identified in response to decreasing and then increasing the power. A set of memory cells is then selected from the identified memory cells to use in hardware security.

Abstract: A method includes setting an output of each memory cell in an array of memory cells to a same first value, decreasing power to the array of memory cells and then increasing power to the array of memory cells. Memory cells in the array of memory cells with outputs that switched to a second value different from the first value are then identified in response to decreasing and then increasing the power. A set of memory cells is then selected from the identified memory cells to use in hardware security.

Abstract: An apparatus includes a first feed-forward PUF, a second feed-forward PUF and an exclusive-or circuit configured to perform an exclusive-or operation of an output of the first feed-forward PUF and an output of the second feed-forward PUF.

Abstract: An apparatus includes a trigger generator and at least one multiplexer. The trigger generator is configured to generate a non-periodic trigger output. The at least one multiplexer is configured to output a valid control signal and an obfuscated control signal in response to a key value input. The obfuscated control signal is selectively set to one of a valid control signal and an invalid control signal based on the non-periodic trigger output.

Abstract: The present invention relates to the design and implementation of a seizure detection or prediction system. The proposed invention computes and selects spectral power ratio features, cross-channel spectral power ratio features, cross spectral power features and cross spectral power ratio features in a patient-specific manner. The selected features are input to a classifier to detect or predict seizures. The proposed algorithm takes advantage of high sensitivity in detecting or predicting seizures and low complexity in implementation. The proposed scheme is general and is suitable for creating a trigger for therapy delivery in a closed-loop therapy system. The therapy could involve either delivery of an anti-epileptic drug or electrical or magnetic stimulation of the brain.

Abstract: A method includes setting an output of each memory cell in an array of memory cells to a same first value, decreasing power to the array of memory cells and then increasing power to the array of memory cells. Memory cells in the array of memory cells with outputs that switched to a second value different from the first value are then identified in response to decreasing and then increasing the power. A set of memory cells is then selected from the identified memory cells to use in hardware security.

Abstract: An apparatus includes a finite state machine and a physical structure capable of providing a response to a challenge, the physical structure such that before the physical structure is ever provided with the challenge, the response to the challenge is unpredictable. The finite state machine moves from an initial state to an intermediate state due to receiving the response from the physical structure, and moves from the intermediate state to a final state due to receiving a key. The final state indicates whether the physical structure is a counterfeit physical structure.

Abstract: An apparatus includes a trigger generator and at least one multiplexer. The trigger generator is configured to generate a non-periodic trigger output. The at least one multiplexer is configured to output a valid control signal and an obfuscated control signal in response to a key value input. The obfuscated control signal is selectively set to one of a valid control signal and an invalid control signal based on the non-periodic trigger output.

Abstract: An apparatus includes a finite state machine and a physical structure capable of providing a response to a challenge, the physical structure such that before the physical structure is ever provided with the challenge, the response to the challenge is unpredictable. The finite state machine moves from an initial state to an intermediate state due to receiving the response from the physical structure, and moves from the intermediate state to a final state due to receiving a key. The final state indicates whether the physical structure is a counterfeit physical structure.

Abstract: The present invention relates to the design and implementation of a seizure detection system. In this invention, a reliable way to detect seizures is presented. The proposed invention filters an EEG signal by a Prediction Error Filter. The output of the prediction error filter is subjected to wavelet decomposition. Various features are then extracted from the wavelet coefficients. These features are input to a classifier to detect seizures. The proposed algorithm takes advantage of high sensitivity in detecting seizures and low complexity in implementation. The proposed scheme is general and is suitable for creating a trigger for therapy delivery in a closed-loop therapy system. The therapy could involve either delivery of an anti-epileptic drug or electrical or magnetic stimulation of the brain.

Abstract: The present invention relates to the design and implementation of a three stage computer-aided screening system that analyzes fundus images with varying illumination and fields of view, and generates a severity grade for diabetic retinopathy (DR) using machine learning. In the first stage, bright and red regions are extracted from the fundus image. An optic disc has similar structural appearance as bright lesions, and the blood vessel regions have similar pixel intensity properties as the red lesions. Hence, the region corresponding to the optic disc is removed from the bright regions and the regions corresponding to the blood vessels are removed from the red regions. This leads to an image containing bright candidate regions and another image containing red candidate regions. In the second stage, the bright and red candidate regions are subjected to two-step hierarchical classification. In the first step, bright and red lesion regions are separated from non-lesion regions.

Abstract: The present invention relates to data processing techniques in multi-channel data transmission systems. In this invention, a novel approach is proposed to deal with FEXT interferences in the application of high/ultra-high speed Ethernet systems. Compared with the traditional FEXT cancellation approaches, the proposed FEXT canceller can deal with the non-causal part of FEXT, and thus can achieve better cancellation performance. Instead of using the conventional DFE, structure, TH precoding technique is incorporated into the proposed design to alleviate the error propagation problem. The resulting FEXT cancellers do not contain feedback loops which makes the high speed VLSI implementation easy. A modified design is also developed by using a finite signal as the input to the FEXT canceller such that the hardware complexity of the proposed FEXT canceller can be reduced.

Abstract: The present invention relates to design and implementation of low complexity adaptive echo and NEXT cancellers in multi-channel data transmission systems. In this invention, a highly efficient weight update scheme is proposed to reduce the computational cost of the weight update part in adaptive echo and NEXT cancellers. Based on the proposed scheme, the hardware complexity of the weight update part can be further reduced by applying the word-length reduction technique. The proposed scheme is general and suitable for real applications such as design of a low complexity transceiver in 10GBase-T. Different with prior work, this invention considers the complexity reduction in weight update part of the adaptive filters such that the overall complexity of these adaptive cancellers can be significantly reduced.

Abstract: The present invention relates to data processing techniques in multi-channel data transmission systems. In this invention, a method to efficiently deal with FEXT is proposed and a circuit architecture to implement the proposed MIMO-THP equalizer is developed for the application of high/ultra-high speed Ethernet systems. The proposed method relies on the fact that FEXT inherently contains information about the symbols transmitted from the far end transmitters and it can be viewed as a signal rather than noise. Compared with the traditional FEXT cancellation approaches, the proposed design inherits both advantages of MIMO equalization technique and TH precoding technique, thus having better performance. Unlike the existing MIMO-THP technology, the proposed design completely removes the feedback loops in the existing MIMO-THP architecture. Therefore, pipelining techniques can be easily applied to obtain a high-speed design of a multi-channel DSP transceiver.

Abstract: Various systems and methods related to equalization precoding in a communications channel are disclosed. In one implementation precoding is performed on signals transmitted over an optical channel. In one implementation precoding and decoding operations are performed in parallel to facilitate high speed processing in relatively low cost circuits. Initialization of the precoders may be realized by transmitting information related to the characteristics of the channel between transceiver pairs.

Abstract: Secure Variable Data Rate Transceivers and methods for implementing Secure Variable Data Rate are presented. An efficient and systematic method and circuit for implementing secure variable data rate transceivers are presented. The SVDR method is based on block ciphers. An index method is presented for minimizing transmission overhead. This allows SVDR to achieve higher security by using the full ciphermode stream.