Abstract: Disclosed is a system for retinal imaging. The type of image to be captured is selected by a user. Corresponding fixation stimulus is displayed on a fixation screen of the disclosed device for the subject to fix their gaze on. The device comprises illumination sources and, illumination optics and imaging optics, a 3-D accelerometer, and a camera. Signal from the 3-D accelerometer, and the video of the eye of the subject captured by camera are used by a computing device that uses AI techniques to vary the position of the fixation stimulus to obtain a stabilized image of the eye of the subject. The position of the fixation stimulus is varied to compensate for the movement of the handheld device to obtain a stabilized retinal image. Once stabilized, the image is captured.

Abstract: A technique for controlling a target device via a virtual interface, the method including receiving a control input from a virtual interface, determining a control signal based on the control input for an operation to be performed by a first device that is configured to be controlled wirelessly, and transmitting the control signal to the first device to cause the first device to perform the operation.

Abstract: A technique for controlling a target device via a virtual interface, the method including receiving a control input from a virtual interface, determining a control signal based on the control input for an operation to be performed by a first device that is configured to be controlled wirelessly, and transmitting the control signal to the first device to cause the first device to perform the operation.

Abstract: A database system includes a database server, a DRAM, a persistent memory, and at least one storage media. The database server includes a cache manager. The DRAM stores a buffer hash table and the persistent memory includes a persistent memory database cache including a plurality of buffers. Buffer content in a buffer is conditionally persisted subsequent to a system initialization event based on the respective buffer satisfying one or more predefined conditions. Each buffer is associated with buffer descriptor values corresponding to a plurality of buffer descriptors. The plurality of buffer descriptors includes a first type of buffer descriptors and a second type of buffer descriptors. Modifications to the buffer hash table are routed to the DRAM, and modifications to the buffer content and modifications to buffer descriptor values corresponding to the first type of buffer descriptors are explicitly flushed to the persistent memory database cache.

Abstract: A thin film wiring scheme on a substrate. The thin film wiring scheme includes a plurality of chip connection pads at each of a first and second chip site on the substrate, a plurality of directional wiring lines interspersed between the chip connection pads at each of the first and second chip sites, at least one of the directional wiring lines being orthogonal to at least one of the other directional wiring lines at each of the first and second chip sites, and a plurality of chip site interconnection lines connecting directional wiring lines at the first chip site with the directional wiring lines at the second chip site.

Abstract: A device includes a ceramic substrate. A ceramic via is defined within the ceramic substrate at an actual location which differs from a designed desired location for the ceramic via. A minimal capture pad electrically communicates the actual location with the designed desired location. The minimal capture pad contains a ceramic via contact portion, a thin film stud contact portion, and a connecting portion; and each of the three is configured to be as small as permitted to limit the capacitances produced by the capture pad.

Abstract: A multi-layer thin film structure having defined repair lines thereon and a method for repairing interconnections in the multi-layer thin film structure (MLTF) and/or making engineering charges (EC) are provided. The method comprises determining any interconnection defects in the MLTF at a thin film layer adjacent the top metal layer of the structure, using lithography, e.g., direct write expose technology, to define the top surface connections needed to repair the interconnections and/or make EC's, and forming the top surface metallization and repair lines using additive or substractive metallization techniques.

Abstract: The present invention provides an apparatus and process for plasma cleaning the interior surfaces of semiconductor processing chambers. The method is directed to the dry etching of accumulated contaminant residues attached to the inner surfaces of the plasma processing chamber and includes introducing a cleaning gas mixture of a halogen-containing gas; activating a plasma in an environment substantially free of oxygen species; contacting the contaminant residues with the activated cleaning gas to volatilize the residues; and removing the gaseous by-products from the chamber. The etchant gaseous mixture comprises an even or greater amount of at least one fluorine-containing gas and an even or lesser amount of at least one chlorine-containing gas. The instant invention enables the intermittent use of the cleaning steps in an ongoing plasma processing of semiconductor wafers without chamber downtime and significant loss of wafer production.

Abstract: A multi-layer thin film structure having defined repair lines thereon and a method for repairing interconnections in the multi-layer thin film structure (MLTF) and/or making engineering charges (EC) are provided. The method comprises determining any interconnection defects in the MLTF at a thin film layer adjacent the top metal layer of the structure, using lithography, e.g., direct write expose technology, to define the top surface connections needed to repair the interconnections and/or make EC's, and forming the top surface metallization and repair lines using additive or substractive metallization techniques.

Abstract: A device includes a ceramic substrate. A ceramic via is defined within the ceramic substrate at an actual location which differs from a designed desired location for the ceramic via. A minimal capture pad electrically communicates the actual location with the designed desired location. The minimal capture pad contains a ceramic via contact portion, a thin film stud contact portion, and a connecting portion; and each of the three is configured to be as small as permitted to limit the capacitances produced by the capture pad.

Abstract: A thin-film arrangement for a non-planar structure is described. The structure includes a substrate and a plurality of thin-film layers stacked on top of each other above the substrate. The layers contain conductive patterns and vias that provide connections between the conductive pattern in one of the layers to the conductive pattern in another layer. Vias that provide a connection between the conductive pattern of one layer to the conductive pattern in another remotely located layer are offset and in contact with respect to each other and are positioned in a non-linear arrangement, preferably in the form of a helix or a multiple helix.