Abstract: A method of assembling a semiconductor package includes attaching a semiconductor die to a frame having a strip or panel form. The semiconductor die has at least one stud bump. The die and the stud bump are covered with a first encapsulation material, and then at least a portion of the stud bump is exposed. At least one die conductive member is formed on the first encapsulation material and electrically coupled to the stud bump. The die conductive member is covered with a second encapsulation material, and then at least a portion of the die conductive member is exposed. At least one grid array conductive member is formed on the second encapsulation material and electrically coupled to the die conductive member. Finally, at least one solder ball is attached to the at least one grid array conductive member.

Abstract: A semiconductor package includes a substrate, a die mounted on a first side of the substrate, an array of solder balls mounted on a second, opposite side of the substrate, and a signal-routing structure mounted on the first side of the substrate and adjacent to the die. The substrate and the signal-routing structure provide electrical connections between die pads on the die and some of the solder balls.

Abstract: A method of assembling a semiconductor package includes attaching a semiconductor die to a frame having a strip or panel form. The semiconductor die has at least one stud bump. The die and the stud bump are covered with a first encapsulation material, and then at least a portion of the stud bump is exposed. At least one die conductive member is formed on the first encapsulation material and electrically coupled to the stud bump. The die conductive member is covered with a second encapsulation material, and then at least a portion of the die conductive member is exposed. At least one grid array conductive member is formed on the second encapsulation material and electrically coupled to the die conductive member. Finally, at least one solder ball is attached to the at least one grid array conductive member.

Abstract: A semiconductor device includes a semiconductor die having first and second opposing main surfaces and a die bonding pads on the first main surface, and a conductive member having first and second opposing main surfaces that surrounds the die. The die and the conductive member are encapsulated with a first encapsulant and form an expanded die. The expanded die is mounted on a lead frame having conductive leads, and the conductive leads are electrically coupled to the conductive member, which acts as a power bar, and to the die bonding pads. The conductive member also is electrically coupled to at least one of the die bonding pads. The expanded die and portions of the conductive leads are encapsulated with a second encapsulant.

Abstract: In a packaged semiconductor device, a die is mounted on a substrate having power connection pads. An exterior (e.g., top) surface of the die has power bond pads and distributed power feed pads. Bond wires electrically connect the power connection pads of the substrate to the power bond pads of the die, and exterior conductive structures electrically connect the power bond pads of the die to the distributed power feed pads of the die. The exterior conductive structures are printed or pasted onto the exterior die surface. Using exterior conductive structures instead of interior conductive traces (in the die) reduces resistive power losses and frees up more room for routing signals within the interior die layers.

Abstract: A method for assembling a 3D integrated circuit package that includes a base device and a top device. The method includes bonding (i) a pre-formed via array having a via rack and via elements and (ii) a base die to the substrate of the base device. The resulting sub-assembly is encapsulated in molding compound, and the via rack and any corresponding molding compound are removed, such as by grinding, to generate a base device with vias corresponding to the via elements and exposed bond posts on its top surface corresponding to the tops of the vias. A pre-packaged or unpackaged top device is then attached and bonded to the base device and, if necessary, encapsulated to form the 3D package with the exposed tops of the vias providing electrical connections between the base substrate and the top device.

Abstract: A method of assembling a semiconductor package includes attaching a semiconductor die to a frame having a strip or panel form. The semiconductor die has at least one stud bump. The die and the stud bump are covered with a first encapsulation material, and then at least a portion of the stud bump is exposed. At least one die conductive member is formed on the first encapsulation material and electrically coupled to the stud bump. The die conductive member is covered with a second encapsulation material, and then at least a portion of the die conductive member is exposed. At least one grid array conductive member is formed on the second encapsulation material and electrically coupled to the die conductive member. Finally, at least one solder ball is attached to the at least one grid array conductive member.

Abstract: A semiconductor sensor die grid array package includes a semiconductor die having an active surface and an opposite backside surface. The active surface has external die connection pads. Conductive runners respectively connect the die connection pads to external connection mounts of the package. An encapsulant covers the semiconductor die. The encapsulant has a base surface proximal to the conductive runners and a stacking surface opposite the base surface. A sensor die is supported on the stacking surface. The sensor die has an active surface and an opposite backside surface that faces the stacking surface, and the sensor active surface has sensor connection pads. Conductive vias engage with the conductive runners and also are wire bonded to one of the sensor connection pads.

Abstract: A method of packaging a semiconductor die includes the use of an embedded ground plane or drop-in embedded unit. The embedded unit is a single, stand-alone unit with at least one cavity. The embedded unit is placed on and within an encapsulation area of a process mounting surface. The embedded unit may have different sizes and shapes and a number of different cavities that can be placed in a predetermined position on a substrate, panel or tape during processing of semiconductor dies that are embedded into redistributed chip package (RCP) or wafer level package (WFL) panels. The embedded unit provides the functionality and design flexibility to run a number of embedded units and semiconductor dies or components having different sizes and dimensions in a single processing panel or batch and reduces die drift, movement or skew during encapsulation and post-encapsulation cure.

Abstract: A stiffened semiconductor die package has a semiconductor die including an integrated circuit. The die has an active side with die bonding pads and an opposite inactive side. A conductive frame that acts as a ground plane surrounds all edges of the die and a mold compound covers the conductive frame and the edges of the die. A thermally conductive sheet is attached to the inactive side of the die. A dielectric support structure with external connector pads with solder deposits is attached to the active side of the die. The external connector pads are selectively electrically coupled to the die bonding pads.

Abstract: A stiffened semiconductor die package has a semiconductor die including an integrated circuit. The die has an active side with die bonding pads and an opposite inactive side. A conductive frame that acts as a ground plane surrounds all edges of the die and a mold compound covers the conductive frame and the edges of the die. A thermally conductive sheet is attached to the inactive side of the die. A dielectric support structure with external connector pads with solder deposits is attached to the active side of the die. The external connector pads are selectively electrically coupled to the die bonding pads.

Abstract: A method of assembling semiconductor devices includes providing a structure that includes an array of conductive frame members beside an array of apertures and an array of conductive vias that are exposed at a first face and extend towards a second face. An array of semiconductor dies is positioned in the array of apertures with their active faces positioned in the first face of the structure. The assembly is encapsulated from the second face of the structure and a redistribution layer is formed on the first face of the structure and the active faces of the die. Material is removed from the back face of the encapsulated array to expose the vias at the back face for connection through a further redistribution layer formed on the back face to electronic components stacked vertically on the further redistribution layer.

Abstract: A surface mount semiconductor device having external contact elements exposed in a ball grid array (BGA) at its external active face for mechanical and electrical connection to an external support and a semiconductor die connected electrically internally with the external contact elements. A reinforcement layer of electrically insulating material extends between and surrounds laterally peripheral contact elements of the BGA. The reinforcement layer extends to from about thirty percent (30%) to about fifty percent (50%) of the height of the peripheral contact elements at the active face.

Abstract: A method of forming a semiconductor package includes providing a support and a first semiconductor die, each having first and second main surfaces. The second main surface of the first die is disposed on the first main surface of the support. Stud bumps are formed on the first main surface of the first die. A surface of a second semiconductor die is bonded to the stud bumps. The first main surface of the first die is wire bonded to the first main surface of the support. The first and second dies, the stud bumps, the bond wire, and at least a portion of the first main surface of the support are encapsulated with a mold compound.

Abstract: A semiconductor device has external, exposed electrical contacts at an device active face and a semiconductor die, which has internal, electrical contacts at a die active face. The exposed contacts are offset from the internal contacts laterally of the device active face. A redistribution layer includes a layer of insulating material and redistribution interconnectors within the insulating material, the interconnectors connecting with the exposed contacts. A set of conductors connect the internal contacts and the interconnectors. The conductors have oblong, tear drop shaped cross-sections extending laterally of the die active face beyond the respective internal contacts, and contact the interconnectors at positions spaced further apart than the internal contacts. The redistribution layer may be prefabricated using less costly manufacturing techniques such as lamination.

Abstract: A stiffened semiconductor die package has a semiconductor die including an integrated circuit. The die has an active side with die bonding pads and an opposite inactive side. A conductive frame that acts as a ground plane surrounds all edges of the die and a mold compound covers the conductive frame and the edges of the die. A thermally conductive sheet is attached to the inactive side of the die. A dielectric support structure with external connector pads with solder deposits is attached to the active side of the die. The external connector pads are selectively electrically coupled to the die bonding pads.

Abstract: A method of making a semiconductor device includes providing a first semiconductor die and a conductive frame member having at least one conductive via. A first encapsulation layer is formed. A first redistribution layer is formed opposite the first encapsulation layer. A second redistribution layer is formed opposite the first redistribution layer. A second semiconductor die is mounted and electrically connected with receptor pads in the second redistribution layer. A third semiconductor die is mounted to the second semiconductor die and electrically connected with bond wires to a conductor in the second redistribution layer. A second encapsulation layer embeds the second and third semiconductor dies, the wires, and the conductor in the second redistribution layer.

Abstract: A method of assembling semiconductor devices includes providing a structure that includes an array of conductive frame members beside an array of apertures and an array of conductive vias that are exposed at a first face and extend towards a second face. An array of semiconductor dies is positioned in the array of apertures with their active faces positioned in the first face of the structure. The assembly is encapsulated from the second face of the structure and a redistribution layer is formed on the first face of the structure and the active faces of the die. Material is removed from the back face of the encapsulated array to expose the vias at the back face for connection through a further redistribution layer formed on the back face to electronic components stacked vertically on the further redistribution layer.

Abstract: A semiconductor device has external, exposed electrical contacts at an device active face and a semiconductor die, which has internal, electrical contacts at a die active face. The exposed contacts are offset from the internal contacts laterally of the device active face. A redistribution layer includes a layer of insulating material and redistribution interconnectors within the insulating material, the interconnectors connecting with the exposed contacts. A set of conductors connect the internal contacts and the interconnectors. The conductors have oblong, tear drop shaped cross-sections extending laterally of the die active face beyond the respective internal contacts, and contact the interconnectors at positions spaced further apart than the internal contacts. The redistribution layer may be prefabricated using less costly manufacturing techniques such as lamination.

Abstract: A method of packaging a semiconductor die includes the use of an embedded ground plane or drop-in embedded unit. The embedded unit is a single, stand-alone unit with at least one cavity. The embedded unit is placed on and within an encapsulation area of a process mounting surface. The embedded unit may have different sizes and shapes and a number of different cavities that can be placed in a predetermined position on a substrate, panel or tape during processing of semiconductor dies that are embedded into redistributed chip package (RCP) or wafer level package (WFL) panels. The embedded unit provides the functionality and design flexibility to run a number of embedded units and semiconductor dies or components having different sizes and dimensions in a single processing panel or batch and reduces die drift, movement or skew during encapsulation and post-encapsulation cure.