Abstract: A semiconductor memory device capable of easily determining where defective memory cells are located by selectively isolating and testing a redundancy memory cell block. In the semiconductor memory device having a redundancy memory cell block for replacing defective cells by redundant memory cells in order to repair the defective cells in a main memory cell block, a normal mode test for testing the main memory cell block and the redundancy memory cell block and a redundancy isolation mode test for selectively isolating and testing the redundancy memory cell block are adopted, and it is determined whether the defective memory cells found by the normal mode test are located in the main memory block or in the redundancy memory cell block by the redundancy isolation mode test.

Abstract: A row decoder driver in a semiconductor memory device includes a first MOS transistor. The first MOS transistor includes a first source area having a width equal to an integral multiple of a memory cell pitch, and a first drain area having a width equal to the integral multiple of the memory cell pitch. The first drain area is adjacent to the first source area with a first gate area formed between the first source area and the first drain area. The gate area and an underlying channel region extend in a direction perpendicular to the direction of a wordline. First source contacts are in the first source area, and first drain contacts are in the first drain area, facing the first source contacts across the first gate area. This placement of source and drain contacts increases the efficiency of the MOS driver. Therefore, important properties such as tRCD and tRP in a synchronous DRAM are improved, and a standby current in the row decoder driver is reduced.

Abstract: A method for arranging I/O lines in a multi-memory bank having, a plurality of memory banks, an I/O sense amplifier block, a plurality of I/O sense amplifiers, a plurality of column-decoder blocks, a plurality of local I/O line pairs, and a plurality of global I/O line pairs. Memory chip operating efficiency is improved, for example, by dividing a plurality of memory banks by an I/O sense amplifier block, alternating the positions of I/O line transfer transistors and sense amplifier driving transistors, and intersecting global I/O line pairs thereby easing bank addressing and enhancing the speed of operation.

Abstract: A semiconductor memory device of the present invention comprises at least two memory cell blocks having a plurality of bit line pairs, respectively, and a plurality of sense amplifier blocks arranged between the memory cell blocks. Each sense amplifier block has two bit line precharge transistors, one equalization, and two bit line isolation transistors. The device further comprises an unit precharge-isolation region which has a) an width in which two bit line pairs are disposed, wherein the transistors are fabricated in the unit precharge-isolation region, b) two active regions arranged in the unit precharge-isolation region, wherein the precharge and equalization transistors are placed in the other of the active regions, and c) five active to bit line contacts arranged in zigzag within the active regions. According to the structure of the present invention, three gate electrodes of the transistors are disposed at the corresponding active regions in "h-l-l" shape.

Abstract: Integrated circuit memory devices include a semiconductor substrate of first conductivity type (e.g., P-type), a first well region of second conductivity type (e.g., N-type) in the substrate and first and second nonoverlapping sub-well regions of first conductivity type in the first well region. To improve the electrical characteristics of circuits within the memory device, a first semiconductor device is provided in the first sub-well region (which is biased at a back-bias potential (Vbb)) and a second semiconductor device is provided in the second sub-well region (which is biased at a ground or negative supply potential (Vss)). The first semiconductor device is preferably selected from the group consisting of memory cell access transistors, equalization circuits and isolation gates. The second semiconductor device is also preferably selected from the group consisting of column select circuits and sense amplifiers.

Abstract: A memory device includes a plurality of data input/output (I/O) lines and means for receiving a column address. The memory device also includes a plurality of primary memory cells, a selected primary memory cell of the plurality of primary memory cells being connected to a primary global I/O line in response to receipt of one column address, and a plurality of redundant memory cells, a selected redundant memory cell of the plurality of redundant memory cells being connected to a redundant global I/O line in response to receipt of the one column address.

Abstract: A voltage boosting circuit is constructed together with a semiconductor memory device on a common substrate in an integrated circuit. The voltage boosting circuit comprises a first oscillating circuit, a boosted voltage Vpp main pumping circuit driven by the first oscillating circuit, a transmission gate for supplying Vpp in response to the output of the Vpp main pumping circuit, and a well bias supplying circuit for supplying a given bias to an isolation well on the substrate in which well the transmission gate is formed. The transmission gate includes a field effect transistor switched in common-source-amplifier configuration, rather than in common-drain-amplifier configuration, which mode of switching avoids unwanted voltage offset attributable to source-follower action.