Abstract: An internal reference voltage generation device may include a cell array including a plurality of cells which provide reference voltages of different levels. Each of the plurality of cells may include one of a plurality of divider resistors included in a resistor string; a transmission gate configured to output a voltage of a divider node which is connected to the one divider resistor, in response to a select signal; and a unit decoder configured to provide the select signal to the transmission gate.

Abstract: A duty cycle correction circuit includes a duty correction circuit, an information generation circuit and a duty control circuit. The duty correction circuit corrects a duty rate of an input clock signal based on a duty control code to generate an output clock signal. The information generation circuit compares a difference between operation power voltages based on an operation mode to generate voltage information. The duty control circuit receives the voltage information from the information generation circuit and generates the duty control code that includes the voltage information based on a duty rate of the output clock signal.

Abstract: The present technology may include a first detection unit configured to generate an output signal by detecting a level of an input terminal in response to a transition of a control clock signal during a normal read operation, and a second detection unit configured to generate the output signal by detecting the level of the input terminal regardless of the transition of the control clock signal during a state information read operation.

Abstract: A duty cycle correction circuit includes a duty correction circuit, an information generation circuit and a duty control circuit. The duty correction circuit corrects a duty rate of an input clock signal based on a duty control code to generate an output clock signal. The information generation circuit compares a difference between operation power voltages based on an operation mode to generate voltage information. The duty control circuit receives the voltage information from the information generation circuit and generates the duty control code that includes the voltage information based on a duty rate of the output clock signal.

Abstract: The present technology may include a first detection unit configured to generate an output signal by detecting a level of an input terminal in response to a transition of a control clock signal during a normal read operation, and a second detection unit configured to generate the output signal by detecting the level of the input terminal regardless of the transition of the control clock signal during a state information read operation.

Abstract: A semiconductor apparatus includes a data input buffer configured to generate write data by receiving data that is input through a data input/output unit during a write operation section and configured to generate an output level detection signal by detecting a voltage level of the data I/O unit during a read operation section.

Abstract: A semiconductor apparatus includes a data input buffer configured to generate write data by receiving data that is input through a data input/output unit during a write operation section and configured to generate an output level detection signal by detecting a voltage level of the data I/O unit during a read operation section.

Abstract: An impedance calibration circuit may include: a first driver having an impedance calibrated according to a first impedance control code, and configured to drive an output terminal according to first data; a second driver having an impedance calibrated according to a second impedance control code, and configured to drive the output terminal according to second data; and an impedance calibration circuit configured to calibrate the first impedance control code to a first target value set to a resistance value of an external resistor, and calibrate the second impedance control code to a second target value different from the resistance value of the external resistor.

Abstract: Provided is a calibration circuit and operating method of the calibration circuit. A calibration circuit includes a first resistor code output circuit and a second resistor code output circuit. The first resistor code output circuit is coupled to an external resistor through an input/output pad, performs a first calibration operation, based on a first resistor value, such that a target voltage applied to a first reference node coupled to the input/output pad has a set voltage level, and outputs a first resistor code as a result obtained by performing the first calibration operation. The second resistor code output circuit receives the target voltage, sets an internal resistor value, based on the first resistor code, performs a second calibration operation, based on a second resistor value different from the first resistor value, and outputs a second resistor code as a result obtained by performing the second calibration operation. The first resistor value is a resistor value of the first resistor.

Abstract: An impedance calibration circuit may include: a first driver having an impedance calibrated according to a first impedance control code, and configured to drive an output terminal according to first data; a second driver having an impedance calibrated according to a second impedance control code, and configured to drive the output terminal according to second data; and an impedance calibration circuit configured to calibrate the first impedance control code to a first target value set to a resistance value of an external resistor, and calibrate the second impedance control code to a second target value different from the resistance value of the external resistor.

Abstract: A data output buffer includes a pull-up main driver outputting output data having a high level through an output pad by performing an emphasis operation according to input data, a pull-down main driver outputting the output data having a low level through the output terminal according to the input data, an active inductor controller selectively outputting an inductor activating voltage by detecting a rising or falling period of the input data, and an active inductor selectively performing a de-emphasis operation on the output terminal in response to the inductor activating voltage.

Abstract: The present disclosure relates to a data out buffer and a memory device having the same. The data out buffer includes a pull-up main driver, coupled between a power supply terminal and an output terminal, configured to output data of a high level; and a pull-down main driver, coupled between the output terminal and a ground terminal, configured to output data of a low level, wherein the pull-up main driver comprises a main pull-up transistor of a first type; and a plurality of first trim transistors, each of a second type.

Abstract: A data output buffer includes a pull-up main driver outputting output data having a high level through an output pad by performing an emphasis operation according to input data, a pull-down main driver outputting the output data having a low level through the output terminal according to the input data, an active inductor controller selectively outputting an inductor activating voltage by detecting a rising or falling period of the input data, and an active inductor selectively performing a de-emphasis operation on the output terminal in response to the inductor activating voltage.

Abstract: The present disclosure relates to a data out buffer and a memory device having the same. The data out buffer includes a pull-up main driver, coupled between a power supply terminal and an output terminal, configured to output data of a high level; and a pull-down main driver, coupled between the output terminal and a ground terminal, configured to output data of a low level, wherein the pull-up main driver comprises a main pull-up transistor of a first type; and a plurality of first trim transistors, each of a second type.

Abstract: A semiconductor device includes a first data transmitting/receiving circuit, a second data transmitting/receiving circuit, and a plurality of channels configured to couple the first and second data transmitting/receiving circuits. The first data transmitting/receiving circuit includes a Tx delay unit configured to transmit data to the plurality of channels, an Rx delay unit configured to receive data from the plurality of channels, and a de-skew control unit configured to control delay amounts of the Tx delay unit and the Rx delay unit according to phase information of reference clock signals received through the plurality of channels.

Abstract: A transmitter operates by receiving a first power supply voltage and a second power supply voltage lower than the first power supply voltage, and includes a driving circuit that generates an output signal according to a driving control signal, a swing adjustment block that adjusts a swing width of the output signal to be lower than a difference between the first power supply voltage and the second power supply voltage in response to a swing control signal, and a swing control signal generation circuit that generates the swing control signal based on the output signal.

Abstract: A transmitter operates by receiving a first power supply voltage and a second power supply voltage lower than the first power supply voltage, and includes a driving circuit that generates an output signal according to a driving control signal, a swing adjustment block that adjusts a swing width of the output signal to be lower than a difference between the first power supply voltage and the second power supply voltage in response to a swing control signal, and a swing control signal generation circuit that generates the swing control signal based on the output signal.

Abstract: A semiconductor device includes a first data transmitting/receiving circuit, a second data transmitting/receiving circuit, and a plurality of channels configured to couple the first and second data transmitting/receiving circuits. The first data transmitting/receiving circuit includes a Tx delay unit configured to transmit data to the plurality of channels, an Rx delay unit configured to receive data from the plurality of channels, and a de-skew control unit configured to control delay amounts of the Tx delay unit and the Rx delay unit according to phase information of reference clock signals received through the plurality of channels.