Patents by Inventor KEUNHO RHEW

KEUNHO RHEW has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor package including stacked chip structure
    Patent number: 11961824
    Abstract: A semiconductor package includes; a package substrate including an upper surface with a bonding pad, a lower semiconductor chip disposed on the upper surface of the package substrate, wherein an upper surface of the lower semiconductor chip includes a connect edge region including a connection pad and an open edge region including a dam structure including dummy bumps, a bonding wire having a first height above the upper surface of the lower semiconductor chip and connecting the bonding pad and the connection pad, an upper semiconductor chip disposed on the upper surface of the lower semiconductor chip using an inter-chip bonding layer, and a molding portion on the package substrate and substantially surrounding the lower semiconductor chip and the upper semiconductor chip.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: April 16, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunggyun Noh, Sangwoo Pae, Jinsoo Bae, Iljoo Choi, Deokseon Choi, Keunho Rhew
  • SEMICONDUCTOR PACKAGE INCLUDING STACKED CHIP STRUCTURE
    Publication number: 20230028943
    Abstract: A semiconductor package includes; a package substrate including an upper surface with a bonding pad, a lower semiconductor chip disposed on the upper surface of the package substrate, wherein an upper surface of the lower semiconductor chip includes a connect edge region including a connection pad and an open edge region including a dam structure including dummy bumps, a bonding wire having a first height above the upper surface of the lower semiconductor chip and connecting the bonding pad and the connection pad, an upper semiconductor chip disposed on the upper surface of the lower semiconductor chip using an inter-chip bonding layer, and a molding portion on the package substrate and substantially surrounding the lower semiconductor chip and the upper semiconductor chip.
    Type: Application
    Filed: February 25, 2022
    Publication date: January 26, 2023
    Inventors: HYUNGGYUN NOH, SANGWOO PAE, JINSOO BAE, ILJOO CHOI, DEOKSEON CHOI, KEUNHO RHEW