Abstract: Disclosed is an analog-to-digital converter including a comparison circuit and a counter circuit. The comparison circuit outputs a comparison result signal based on a pixel signal and a ramp signal and outputs a zero-crossing prediction signal, is the comparison circuit being configured to transition the zero-crossing prediction signal before a zero-crossing time point at which a voltage level of the pixel signal becomes identical to a voltage level of the ramp signal and during a time interval during which the voltage level of the ramp signal is reduced. The counter circuit outputs a low-order bit digital code based on the zero-crossing prediction signal and stops the output of the low-order bit digital code based on the comparison result signal.