Abstract: In various embodiments of the present invention a circuit apparatus having a rounded trace, a method to manufacture the circuit apparatus, and a design structure used in the design, testing, or manufacturing of the circuit apparatus are described. An artwork layer having an adaptable-mask section allows a graded amount of light to pass into an underlying photoresist layer. Subsequent to developing the photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least a portion of a rounded trace. The photoresist layer is removed resulting in a circuit apparatus having a rounded trace.

Abstract: The method includes applying a magnetic etching ferrofluid, that contains an aqueous etchant solution within one or more reverse micelles responsive to a magnetic field, onto the substrate at a first depth. The method also includes creating a magnetic field at a first strength that causes the reverse micelle to move in a first direction at a first rate. The method also includes determining whether the substrate is at a second depth. The method also includes reducing, in response to the substrate being at a second depth, the magnetic field to a second strength to cause the reverse micelle to move in the first direction at a second rate.

Abstract: A system for use with optical and electrical signaling is disclosed. The system may include a printed circuit board (PCB) that includes a plurality of layers vertically stacked between a first face and a second face and a first optical signal transmission path within a first internal layer of the plurality of layers. The PCB may also include an electrical signal transmission path and a via extending through the plurality of layers. The via may include a first reflective surface that is configured to reflect light between the first optical signal transmission path and an opening of the via on the first face and an electrically conductive material that is configured to electrically connect the electrical signal transmission path to a portion of the via on the first face.

Abstract: The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad placed between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip and nanofibers aligned perpendicular to mating surfaces of the first chip and the second chip.

Abstract: Two test coupons are utilized in an apparatus, method and design process/structure for determining the moisture content in an electronic circuit board (e.g., a printed circuit board (PCB) or panel). The first coupon has a laminate stack-up with voltage planes separated from each other by dielectric material. These voltage planes include etched clearances with neither plated through holes (PTHs) nor drilled holes extending therethrough. The second coupon is substantially identical to the first coupon except that each of the voltage planes of the first coupon includes PTHs extending through etched clearances corresponding to the etched clearances of the first coupon. In one embodiment, an alarm indicating unacceptably high moisture content is generated if a delta capacitance calculated as a difference between capacitance measurements acquired from the respective coupons is greater than a threshold. Preferably, the alarm notifies a user that at least one aqueous process related to PTH formation is implicated.

Abstract: Methods and structures are provided for implementing embedded hybrid electrical-optical printed circuit board (PCB) constructs. The embedded hybrid electrical-optical PCB construct includes electrical channels and optical channels within a single physical PCB layer. The embedded hybrid electrical-optical PCB construct includes an electrically conductive sheet or a copper sheet, and a reflective mesh adhesive layer provided with the electrical channels and optical channels within the single physical PCB layer.

Abstract: A method for fabricating a coaxial structure having an electrical conductor surrounded by an optically conductive dielectric is disclosed. The method may include creating an optical trench in an electrical conductor and depositing an optical material into the optical trench to cover an inner surface of the trench. The method may also include removing a portion of the deposited optical material from the optical trench to form an embedded trench in the deposited optical material, and building up electrically conductive material from within the embedded trench to create an inner electrical conductor. The method may also include depositing optical material around an exposed portion of the inner electrical conductor to create an optical channel encapsulating the inner electrical conductor, and depositing electrically conductive material over a top surface of the optical channel and over a top surface of the first electrical conductor to create the coaxial structure.

Abstract: A method and structures are provided for implementing an impedance-matched, low inductance, 3-dimensional (3D) twisted-pair within a given dielectric material layer. A dielectric material layer is loaded with an electrically insulating metal spinel compound at a set loading level. Upon exposure to a focused laser beam, the spinel is converted to a metallic particle with an electrical conductivity suitable for various applications. An impedance-matched, low inductance, 3-dimensional (3D) twisted-pair is generated using a laser direct structuring process with a fine depth control achieved with a laser.

Abstract: A method for fabricating a coaxial structure having an electrical conductor surrounded by an optically conductive dielectric is disclosed. The method may include creating an optical trench in an electrical conductor and depositing an optical material into the optical trench to cover an inner surface of the trench. The method may also include removing a portion of the deposited optical material from the optical trench to form an embedded trench in the deposited optical material, and building up electrically conductive material from within the embedded trench to create an inner electrical conductor. The method may also include depositing optical material around an exposed portion of the inner electrical conductor to create an optical channel encapsulating the inner electrical conductor, and depositing electrically conductive material over a top surface of the optical channel and over a top surface of the first electrical conductor to create the coaxial structure.

Abstract: The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip, and a heat removal device thermally connected to the thermal interface material pad.

Abstract: Methods and structures are provided for implementing embedded hybrid electrical-optical printed circuit board (PCB) constructs. The embedded hybrid electrical-optical PCB construct includes electrical channels and optical channels within a single physical PCB layer. The embedded hybrid electrical-optical PCB construct includes an electrically conductive sheet or a copper sheet, and a reflective mesh adhesive layer provided with the electrical channels and optical channels within the single physical PCB layer.

Abstract: The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors.

Abstract: An impact sensor includes a piezoelectric transducer operatively connected to a chromic device. The chromic device includes a chromic material that changes from a first color state to a second color state in response to electric power generated by the piezoelectric transducer when exposed to a given level of impact force. The chromic material is bistable so that the chromic material remains in the second color state for a significant amount of time. An impact force to which the sensor has been subjected may be quantified by observing the chromic device. In one embodiment, the chromic material is an electrochromic material, such as a viologen, that changes through a color gradient of light transmission states from the first color state to the second color state. A printed color gradient may be used to aid in quantifying the impact force. In another embodiment, the chromic device includes a thermochromic material.

Abstract: A first artwork layer having a first adaptable-mask section allows a graded amount of light to pass into an underlying first photoresist layer. Subsequent to developing the first photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least a lower portion of a rounded trace. A dielectric layer is laminated upon the lower portion and a second artwork layer having an second adaptable-mask section allows a graded amount of light to pass into a second photoresist layer. Subsequent to developing the second photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least an upper portion of a rounded trace. The photoresist and dielectric layers are removed resulting in a circuit apparatus having a rounded differential pair trace.

Abstract: A first artwork layer having a first adaptable-mask section allows a graded amount of light to pass into an underlying first photoresist layer. Subsequent to developing the first photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least a lower portion of a rounded trace. A dielectric layer is laminated upon the lower portion and a second artwork layer having an second adaptable-mask section allows a graded amount of light to pass into a second photoresist layer. Subsequent to developing the second photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least an upper portion of a rounded trace. The photoresist and dielectric layers are removed resulting in a circuit apparatus having a rounded differential pair trace.

Abstract: The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad placed between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip. The method includes creating a first chip with circuitry on a first side and creating a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The method further includes placing a thermal interface material pad between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip.

Abstract: Two test coupons are utilized in an apparatus, method and design process/structure for determining the moisture content in an electronic circuit board (e.g., a printed circuit board (PCB) or panel). The first coupon has a laminate stack-up with voltage planes separated from each other by dielectric material. These voltage planes include etched clearances with neither plated through holes (PTHs) nor drilled holes extending therethrough. The second coupon is substantially identical to the first coupon except that each of the voltage planes of the first coupon includes PTHs extending through etched clearances corresponding to the etched clearances of the first coupon. In one embodiment, an alarm indicating unacceptably high moisture content is generated if a delta capacitance calculated as a difference between capacitance measurements acquired from the respective coupons is greater than a threshold. Preferably, the alarm notifies a user that at least one aqueous process related to PTH formation is implicated.

Abstract: In various embodiments of the present invention a circuit apparatus having a rounded trace, a method to manufacture the circuit apparatus, and a design structure used in the design, testing, or manufacturing of the circuit apparatus are described. An artwork layer having an adaptable-mask section allows a graded amount of light to pass into an underlying photoresist layer. Subsequent to developing the photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least a portion of a rounded trace. The photoresist layer is removed resulting in a circuit apparatus having a rounded trace.

Abstract: A first artwork layer having a first adaptable-mask section allows a graded amount of light to pass into an underlying first photoresist layer. Subsequent to developing the first photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least a lower portion of a rounded trace. A dielectric layer is laminated upon the lower portion and a second artwork layer having an second adaptable-mask section allows a graded amount of light to pass into a second photoresist layer. Subsequent to developing the second photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least an upper portion of a rounded trace. The photoresist and dielectric layers are removed resulting in a circuit apparatus having a rounded differential pair trace.

Abstract: The exemplary embodiments of the present invention provide a method and system for aligning graphite nanofibers in a thermal interface material to enhance the thermal interface material performance. The method includes preparing the graphite nanofibers in a herringbone configuration, and dispersing the graphite nanofibers in the herringbone configuration into the thermal interface material. The method further includes applying a magnetic field of sufficient intensity to align the graphite nanofibers in the thermal interface material. The system includes the graphite nanofibers configured in a herringbone configuration and a means for dispersing the graphite nanofibers in the herringbone configuration into the thermal interface material. The system further includes a means for applying a magnetic field of sufficient intensity to align the graphite nanofibers in the thermal interface material.