Abstract: A portable media encoder is disclosed. A portable media encoder includes a a video input port configured to receive a video input from a video source, an audio input port configured to receive an audio input from an audio source, and a digital output port for providing a digital output stream corresponding to the received video input and audio input. An encoding processor that converts the video input and the audio input into a streamable digital output format for transmitting through the digital output port is provided. A digital control input port for receiving commands from a remote management console and providing the commands to the encoding processor is also provided. A housing enclosed the encoding processor and provides at least one access panel facilitating user access to the video input port, the audio input port, the digital output port, and the digital control input port.

Abstract: A memory module is interposed between a host and a disk drive. The memory module includes a solid-state nonvolatile memory used for caching data sent by the host for storage in the disk drive. Caching takes place under the control of a memory controller in the memory module and may be transparent to the host. The disk drive may remain spun-down when data is cached, saving power. The destination for host data may be determined based on desired speed, power consumption and expected need for that data. A host may send specific commands to the memory module to enable additional functions.

Abstract: Method for a portable memory device is provided. The method includes, recording a keyword and creating a voice based template for the keyword, wherein a processor for the portable memory device creates the voice based template and stores the voice based template in non-volatile memory cells; prompting the user to capture button control actions related to a portable memory device functionality; and associating the button control actions to the voice based template.

Abstract: A portable memory device (“device”) is provided. The device includes a microphone for receiving a voice command from a user; and a device controller that creates a voice based template for the voice command and stores the voice based template in a plurality of non-volatile memory cells, wherein the voice based template is associated with one or more button control actions entered by the user for certain device functionality.

Abstract: A buffer cache interposed between a non-volatile memory and a host may be partitioned into segments that may operate with different policies. Cache policies include write-through, write and read-look-ahead. Write-through and write back policies may improve speed. Read-look-ahead cache allows more efficient use of the bus between the buffer cache and non-volatile memory. A session command allows data to be maintained in volatile memory by guaranteeing against power loss.

Abstract: A portable memory storage device (“device”) is provided. The device includes a microphone for receiving a user voice input; a controller that receives the voice input and creates a template; and a plurality of non-volatile memory cells for storing the template, wherein the template is used to authenticate the user for any subsequent user request for accessing the device and an application is launched when the device interfaces with a host system to enroll the user as an authorized user to access device functionality and/or access host system functionality.

Abstract: Method for a portable memory storage device is provided. The method includes, enrolling the device after the device interfaces with a host system and an application is launched that requests a user to provide voice input; receiving the user voice input and storing the voice input as a template for subsequent user access; wherein the template is stored in non-volatile memory cells of the device; and authenticating a user by receiving user voice input and comparing the voice input with the stored template, wherein access to user files is provided after the user is authenticated.

Abstract: A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data.

Abstract: A non-volatile memory device is provided with a controller and includes method that controls memory operations and to emulate the memory and communication characteristics of a legacy memory device. In this way, the memory device is compatible with a host that was originally designed to operate the legacy memory device. In particular, the controller performs the emulation to the host taking into account differences such as multibit memory, error correction requirement, memory support of overwrites, and erasable block sizes.

Abstract: A non-volatile memory device is provided with a controller and includes method that controls memory operations and to emulate the memory and communication characteristics of a legacy memory device. In this way, the memory device is compatible with a host that was originally designed to operate the legacy memory device. In particular, the controller performs the emulation to the host taking into account differences such as multibit memory, error correction requirement, memory support of overwrites, and erasable block sizes.

Abstract: An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with three data registers and a controller circuit. During a flash program operation, one data register is used to control the program operation, a second register is used to hold the target data value, and a third register is used to load the next sector's data. Subsequent to a flash program operation, a sector's data are read from a flash array into the first data register and compared to the target data stored in the second register. When the data is verified good, the data from the third register is copied into the first and second registers for the next program operation. This creates an improved performance system that doesn't suffer data transfer latency during program operations that require data verification after the program operation is complete. Alternate embodiments perform the comparison using two register implementations and a single register implementations.

Abstract: In a memory array having redundant columns, a scheme allows defective cells to be individually remapped to redundant cells in a redundant column. Redundant cells in one redundant column replace defective cells in multiple non-redundant columns. Remapping is done as part of initial test and configuration. Specific hardware can be used for the scheme or firmware in the memory controller can implement the scheme.

Abstract: In a memory array having redundant columns, a scheme allows defective cells to be individually remapped to redundant cells in a redundant column. Redundant cells in one redundant column replace defective cells in multiple non-redundant columns. Remapping is done as part of initial test and configuration. Specific hardware can be used for the scheme or firmware in the memory controller can implement the scheme.

Abstract: A memory module is interposed between a host and a disk drive. The memory module includes a solid-state nonvolatile memory used for caching data sent by the host for storage in the disk drive. Caching takes place under the control of a memory controller in the memory module and may be transparent to the host. The disk drive may remain spun-down when data is cached, saving power. The destination for host data may be determined based on desired speed, power consumption and expected need for that data. A host may send specific commands to the memory module to enable additional functions.

Abstract: The present invention allows for an increase in programming parallelism in a non-volatile memory system without incurring additional data transfer latency. Data is transferred from a controller to a first memory chip and a programming operation is caused to begin. While that first memory chip is busy performing that program operation, data is transferred from the controller to a second memory chip and a programming operation is caused to begin in that chip. Data transfer can begin to the first memory chip again once it has completed its programming operation even though the second chip is still busy performing its program operation. In this manner high parallelism of programming operation is achieved without incurring the latency cost of performing the additional data transfers.

Abstract: Methods and apparatus for performing wear leveling in a non-volatile memory system are disclosed. Included is a method for performing wear leveling in a memory system that includes a first zone, which has a first memory element that includes contents, and a second zone includes identifying the first memory element and associating the contents of the first memory element with the second zone while disassociating the contents of the first memory element from the first zone. In one embodiment, associating the contents of the first memory element with the second involves moving contents of a second memory element into a third memory element, then copying the contents of the first memory element into the second memory element.

Abstract: A non-volatile memory is divided into logical zones by the card controller in order reduce the size of the data structures it uses for address translation. Zone boundaries are adjusted to accommodate defects allowed by memory test to improve card yields and to adjust boundaries in the field to extend the usable lifetime of the card. Firmware scans for the presence of defective blocks on the card. Once the locations of these blocks are known, the firmware calculates the zone boundaries in such a way that good blocks are equally distributed among the zones. Since the number of good blocks meets the card test criteria by the memory test criteria, defects will reduce card yield fallout. The controller can perform dynamic boundary adjustments. When defects occur, the controller can perform the analysis again and, if needed, redistributes the zone boundaries, moving any user data.

Abstract: A portable memory storage device is disclosed where access to information on the device is granted only upon proper biometric authentication of a user. The device includes a controller, a non-volatile memory which may be a flash memory, and a biometric scanner system for controlling access to the information within the non-volatile memory. Each of the controller, non-volatile memory and biometric scanner system may be mounted in a base of the portable device, with the biometric system having an exposed surface on a top portion of the base for accepting biometric data such as a fingerprint. A cover is provided which includes a USB connector capable of mating within a USB port of the host device to establish communications between the portable and host devices. The cover also covers the exposed portion of the biometric scanner to protect the sensor when the portable memory storage device is not in use.

Abstract: The on-chip copy process is extended so that the data may be copied between two blocks that may be on different chips, different planes on the same chip, or the same plane of the same chip. More specifically, the methods described here provide a single data copying mechanism that allows data to be copied between any two locations in a memory system. An exemplary embodiment uses an EDO-type timing. According to another aspect, selected portions of the relocated data, such as chosen words in a transferred page, can be updated in the controller on the fly. In addition to transferring a data set directly from a read buffer of a source array to a write buffer of a destination array, the data set can concurrently be copied, if desired, into the controller where an error detection and correction operation can be performed on it.

Abstract: A method of programming a non-volatile memory array using an on-chip write cache is disclosed. Individual data packets received by the memory system are stored in cache memory. More than one data packet may be stored in this way and then programmed to a single page of the non-volatile array. This results in more efficient use of storage space in the non-volatile array.