Patents by Inventor Kevin Cota
Kevin Cota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7390680Abstract: A method and system for selectively identifying reliability risk die based on characteristics of local regions on a wafer by computing particle sensitive yield and using the particle sensitive yield to identify reliability risk die. Specifically, a bin characteristics database which identifies hard and soft bins that are sensitive to different failure mechanisms is maintained, and the bin characteristics database is used to compute particle sensitive yield. It is determined whether the particle sensitive yield of the local region around the current die is less than a pre-set threshold, and the die is downgraded if the particle sensitive yield of the local region around the current die is less than the pre-set threshold. If the particle sensitive yield of the local region around the current die is not less than the pre-set threshold, the die is not downgraded.Type: GrantFiled: January 6, 2005Date of Patent: June 24, 2008Assignee: LSI CorporationInventors: Ramon Gonzales, Kevin Cota, Manu Rehani, David Abercrombie
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Patent number: 7305634Abstract: A method and system of selectively identifying at risk die based on location within the reticle. Reticle and stepping information is stored in a database. All reticle shots in a wafer and in a lot are overlaid on top of each other. The reticle and stepping information is used to calculate pass/fail or specific bin yield of reticle fields. It is determined if the yield of some reticle locations is below a statistical measure by a pre-determined threshold, and if so, all the die in that location are downgraded. The statistical value to compare against does not have to be based on the reticle alone. It can be a wafer of lot level statistic. The process can be applied at a lot or wafer level, or both.Type: GrantFiled: November 23, 2004Date of Patent: December 4, 2007Assignee: LSI CorporationInventors: Manu Rehani, Kevin Cota, Robert Madge
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Publication number: 20060109462Abstract: A method and system of selectively identifying at risk die based on location within the reticle. Reticle and stepping information is stored in a database. All reticle shots in a wafer and in a lot are overlaid on top of each other. The reticle and stepping information is used to calculate pass/fail or specific bin yield of reticle fields. It is determined if the yield of some reticle locations is below a statistical measure by a pre-determined threshold, and if so, all the die in that location are downgraded. The statistical value to compare against does not have to be based on the reticle alone. It can be a wafer of lot level statistic. The process can be applied at a lot or wafer level, or both.Type: ApplicationFiled: November 23, 2004Publication date: May 25, 2006Inventors: Manu Rehani, Kevin Cota, Robert Madge
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Patent number: 6943042Abstract: A method of detecting spatially correlated variations that may be used for detecting statistical outliers in a production lot of integrated circuits to increase the average service life of the production lot includes measuring a selected parameter of each of a plurality of electronic circuits replicated on a common surface; calculating a difference between a value of the selected parameter at a target location and a value of the selected parameter an identical relative location with respect to the target location for each of the plurality of electronic circuits to generate a distribution of differences; calculating an absolute value of the distribution of differences; and calculating an average of the absolute value of the distribution of differences to generate a representative value for the residual for the identical relative location.Type: GrantFiled: August 13, 2003Date of Patent: September 13, 2005Assignee: LSI Logic CorporationInventors: Robert Madge, Kevin Cota, Bruce Whitefield
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Publication number: 20050145841Abstract: A method and system for selectively identifying reliability risk die based on characteristics of local regions on a wafer by computing particle sensitive yield and using the particle sensitive yield to identify reliability risk die. Specifically, a bin characteristics database which identifies hard and soft bins that are sensitive to different failure mechanisms is maintained, and the bin characteristics database is used to compute particle sensitive yield. It is determined whether the particle sensitive yield of the local region around the current die is less than a pre-set threshold, and the die is downgraded if the particle sensitive yield of the local region around the current die is less than the pre-set threshold. If the particle sensitive yield of the local region around the current die is not less than the pre-set threshold, the die is not downgraded.Type: ApplicationFiled: January 6, 2005Publication date: July 7, 2005Inventors: Ramon Gonzales, Kevin Cota, Manu Rehani, David Abercrombie
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Patent number: 6880140Abstract: A method and system for selectively identifying reliability risk die based on characteristics of local regions on a wafer by computing particle sensitive yield and using the particle sensitive yield to identify reliability risk die. Specifically, a bin characteristics database which identifies hard and soft bins that are sensitive to different failure mechanisms is maintained, and the bin characteristics database is used to compute particle sensitive yield. It is determined whether the particle sensitive yield of the local region around the current die is less than a pre-set threshold, and the die is downgraded if the particle sensitive yield of the local region around the current die is less than the pre-set threshold. If the particle sensitive yield of the local region around the current die is not less than the pre-set threshold, the die is not downgraded.Type: GrantFiled: June 4, 2003Date of Patent: April 12, 2005Assignee: LSI Logic CorporationInventors: Ramon Gonzales, Kevin Cota, Manu Rehani, David Abercrombie
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Publication number: 20040249598Abstract: A method and system for selectively identifying reliability risk die based on characteristics of local regions on a wafer by computing particle sensitive yield and using the particle sensitive yield to identify reliability risk die. Specifically, a bin characteristics database which identifies hard and soft bins that are sensitive to different failure mechanisms is maintained, and the bin characteristics database is used to compute particle sensitive yield. It is determined whether the particle sensitive yield of the local region around the current die is less than a pre-set threshold, and the die is downgraded if the particle sensitive yield of the local region around the current die is less than the pre-set threshold. If the particle sensitive yield of the local region around the current die is not less than the pre-set threshold, the die is not downgraded.Type: ApplicationFiled: June 4, 2003Publication date: December 9, 2004Inventors: Ramon Gonzales, Kevin Cota, Manu Rehani, David Abercrombie
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Patent number: 6807655Abstract: A method for adaptively providing parametric limits to identify defective die quantizes the die into a plurality of groups according to statistical distributions, such as intrinsic speed in one embodiment. For each quantization level, an intrinsic distribution of the parameter is derived. Adaptive screening limits are then set as a function of the intrinsic distribution. Dies are then screened according to their parametric values with respect to the adaptive limits.Type: GrantFiled: July 16, 2002Date of Patent: October 19, 2004Assignee: LSI Logic CorporationInventors: Manu Rehani, Kevin Cota, David Abercrombie, Robert Madge
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Patent number: 6787379Abstract: A method of detecting spatially correlated variations that may be used for detecting statistical outliers in a production lot of integrated circuits to increase the average service life of the production lot includes measuring a selected parameter of each of a plurality of electronic circuits replicated on a common surface; calculating a difference between a value of the selected parameter at a target location and a value of the selected parameter an identical relative location with respect to the target location for each of the plurality of electronic circuits to generate a distribution of differences; calculating an absolute value of the distribution of differences; and calculating an average of the absolute value of the distribution of differences to generate a representative value for the residual for the identical relative location.Type: GrantFiled: December 12, 2001Date of Patent: September 7, 2004Assignee: LSI Logic CorporationInventors: Robert Madge, Kevin Cota, Bruce Whitefield
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Patent number: 6782500Abstract: A method for testing integrated circuits, where a predetermined set of input vectors is introduced as test input into the integrated circuits. The output from the integrated circuits in response to the predetermined set of input vectors is sensed, and the output from the integrated circuits is recorded in a wafer map, referenced by position designations. The recorded output for the integrated circuits is mathematically manipulated, and the recorded output for each of the integrated circuits is individually compared to the mathematically manipulated recorded output for the integrated circuits. Graded integrated circuits that have output that differs from the mathematically manipulated recorded output for the integrated circuits by more than a given amount are identified, and a classification is recorded in the wafer map for the graded integrated circuits, referenced by the position designations for the graded integrated circuits.Type: GrantFiled: August 15, 2000Date of Patent: August 24, 2004Assignee: LSI Logic CorporationInventors: Robert J. Madge, Emery Sugasawara, W. Robert Daasch, James N. McNames, Daniel R. Bockelman, Kevin Cota
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Publication number: 20040033635Abstract: A method of detecting spatially correlated variations that may be used for detecting statistical outliers in a production lot of integrated circuits to increase the average service life of the production lot includes measuring a selected parameter of each of a plurality of electronic circuits replicated on a common surface; calculating a difference between a value of the selected parameter at a target location and a value of the selected parameter an identical relative location with respect to the target location for each of the plurality of electronic circuits to generate a distribution of differences; calculating an absolute value of the distribution of differences; and calculating an average of the absolute value of the distribution of differences to generate a representative value for the residual for the identical relative location.Type: ApplicationFiled: August 13, 2003Publication date: February 19, 2004Inventors: Robert Madge, Kevin Cota, Bruce Whitefield
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Patent number: 6598194Abstract: A method for testing integrated circuits having associated position designations, where a predetermined set of input vectors is introduced as test input into the integrated circuits. The output from the integrated circuits in response to the predetermined set of input vectors is sensed, and the output from the integrated circuits is recorded in a wafer map, referenced by the position designations. The output from at least a subset of the integrated circuits is selected and mathematically manipulated to produce a reference value. The output for each of the integrated circuits in the selected subset is individually compared to the reference value, and graded integrated circuits within the selected subset that have output that differs from the reference value by more than a given amount are identified. A classification is assigned to the graded integrated circuits and recorded in the wafer map, referenced by the position designations for the graded integrated circuits.Type: GrantFiled: August 18, 2000Date of Patent: July 22, 2003Assignee: LSI Logic CorporationInventors: Robert J. Madge, Emery Sugasawara, W. Robert Daasch, James N. McNames, Daniel R. Bockelman, Kevin Cota