Abstract: Techniques for estimating a risk of incorrect timing analysis results for signal paths having cells with inputs tied together are described. Signal paths having cells with tied input pins are identified in a circuit. A timing analysis on the signal paths is run to identify the worst case delay through the signal paths. The risk to the signal paths of incorrect timing analysis results due to the cells with tied input pins is estimated by a tied input pin analysis tool. Metrics that quantify timing failure risk associated with signal paths is provided in the form of a set of equations. These equations are embedded into a process allowing automated multi-modal, multi power voltage temperature analysis for the identification of high risk paths.

Abstract: A memory system is described, where the transmission time of data between memory modules is managed so that the overall time delay between specified points in the memory system is maintained a constant. Each lane of a multilane bus may be separately managed, and a data frame evaluated at the destination module, without a need for deskewing at intermediate modules. The time delay in propagation of the data through a module, which may have a switch to route the data, is reduced by operating the data path through the module at one or more submultiples of the bus serial data rate, and selecting the sampling point of the received data so that variations in time delay due to temperature changes or ageing are accommodated.

Abstract: A memory system is described, where the transmission time of data between memory modules is managed so that the overall time delay between specified points in the memory system is maintained a constant. Each lane of a multilane bus may be separately managed, and a data frame evaluated at the destination module, without a need for deskewing at intermediate modules. The time delay in propagation of the data through a module, which may have a switch to route the data, is reduced by operating the data path through the module at one or more submultiples of the bus serial data rate, and selecting the sampling point of the received data so that variations in time delay due to temperature changes or ageing are accommodated.

Abstract: A memory circuit card is described, where the electrical and physical interface between the circuit card and a motherboard bus is independent of the memory type installed on the circuit card. The power supply voltage provided by the mother board is independent of the memory type, and persistent and non-persistent memory types may be used on a plurality of circuit cards installed on the motherboard. The power status of at least portions of the interfaces of the circuit card may be controlled at a future time based on signals received at an input of circuit card.

Abstract: Techniques for estimating a risk of incorrect timing analysis results for signal paths having cells with inputs tied together are described. Signal paths having cells with tied input pins are identified in a circuit. A timing analysis on the signal paths is run to identify the worst case delay through the signal paths. The risk to the signal paths of incorrect timing analysis results due to the cells with tied input pins is estimated by a tied input pin analysis tool. Metrics that quantify timing failure risk associated with signal paths is provided in the form of a set of equations. These equations are embedded into a process allowing automated multi-modal, multi power voltage temperature analysis for the identification of high risk paths.

Abstract: Techniques for estimating a risk of incorrect timing analysis results for signal paths having cells with inputs tied together are described. Signal paths having cells with tied input pins are identified in a circuit. A timing analysis on the signal paths is run to identify the worst case delay through the signal paths. The risk to the signal paths of incorrect timing analysis results due to the cells with tied input pins is estimated by a tied input pin analysis tool. Metrics that quantify timing failure risk associated with signal paths is provided in the form of a set of equations. These equations are embedded into a process allowing automated multi-modal, multi power voltage temperature analysis for the identification of high risk paths.

Abstract: A scheduling apparatus flexibly integrates guaranteed-bandwidth (GB) and best-effort (BE) flows and comprises a combination of a primary weighted-round-robin (WRR) scheduler (PWS) and a secondary WRR scheduler (SWS). The PWS distributes service to the individual GB flows and determines the amount of service that the BE flow aggregate should receive during each frame. The SWS takes care of fairly distributing the service share of the BE aggregate over the individual BE flows. The scheduling apparatus divides the service frame in two subframes. In the first subframe, the PWS fulfills the bandwidth requirements of the GB flows. In the second subframe, the SWS distributes fair service to the BE flows. For each frame, the duration depends on the amount of bandwidth allocated to the GB flows and on the number of GB flows that are backlogged at the beginning of the frame. The amount of bandwidth globally available to BE flows (i.e.

Abstract: A scheduler apparatus provides bandwidth guarantees to individual data packet flows as well as to aggregations of those flows (referred to as “bundles”) in a completely transparent manner, i.e., without using any additional scheduling structure. For each bundle, the scheduler determines the ratio between the bandwidth nominally allocated to the bundle and the sum of the individual bandwidth allocations of the flows that are currently backlogged in the bundle. The scheduler uses that ratio to modulate the timestamp increments that regulate the distribution of bandwidth to the individual flows. In this manner, the greater the ratio for that bundle, the more the bandwidth that each backlogged flow in the bundle receives.

Abstract: A scheduler apparatus provides bandwidth guarantees to individual data packet flows as well as to aggregations of those flows (referred to as “bundles”) in a completely transparent manner, i.e., without using any additional scheduling structure. For each bundle, the scheduler determines the ratio between the bandwidth nominally allocated to the bundle and the sum of the individual bandwidth allocations of the flows that are currently backlogged in the bundle. The scheduler uses that ratio to modulate the timestamp increments that regulate the distribution of bandwidth to the individual flows. In this manner, the greater the ratio for that bundle, the more the bandwidth that each backlogged flow in the bundle receives.

Abstract: A scheduling apparatus flexibly integrates guaranteed-bandwidth (GB) and best-effort (BE) flows and comprises a combination of a primary weighted-round-robin (WRR) scheduler (PWS) and a secondary WRR scheduler (SWS). The PWS distributes service to the individual GB flows and determines the amount of service that the BE flow aggregate should receive during each frame. The SWS takes care of fairly distributing the service share of the BE aggregate over the individual BE flows. The scheduling apparatus divides the service frame in two subframes. In the first subframe, the PWS fulfills the bandwidth requirements of the GB flows. In the second subframe, the SWS distributes fair service to the BE flows. For each frame, the duration depends on the amount of bandwidth allocated to the GB flows and on the number of GB flows that are backlogged at the beginning of the frame. The amount of bandwidth globally available to BE flows (i.e.

Abstract: An electronic system having a backplane defining a plurality of slots each for demountably holding a respective one of a plurality of plug-in modules. The backplane includes a power trace extending to all of the slots for supplying power to all of the slots and a signal trace for carrying a daisy-chained signal to all of the slots. Associated with each of the slots is an arrangement for selectively bypassing the daisy-chained signal past the slot when no module is present in that slot. The arrangement comprises a controllable signal transmission device coupled to the signal trace for selectively providing a conductive path bypassing the slot and a current sensing switch coupled to a branch of the power trace which extends to the slot. The current sensing switch is responsive to current flow through the power trace to the slot for controlling the transmission device to close the conductive path in the absence of current flow and to open the conductive path in the presence of current flow.