Abstract: A multiprocessor system on a chip (MPSoC) implements parallel processing and include a plurality of cores with inter-core communication. This communication is implemented by an on-chip switch fabric in communication with each core, or by shared memory in communication with each core. In another embodiment, a parallel processing system is implemented as a Howard Cascade and uses shared memory for implementing inter-chip communication.

Abstract: A parallel processing computer is described that has several processing devices of several different processing device types each communicating over a computer network. The computer has at least one conversion device in communication with the processing devices, the conversion device being a processing device having conversion code for translating at least some task allocation and other messages from a format understood by the conversion device into a format understood for execution by a particular type of the several types of the processing devices. The computer also has at least one access device in communication with the at least one conversion device, the access device having program code for allocating tasks to processing devices and generating task allocation messages to processing devices. The computer network in an embodiment involves portions of the cellular telephone network as well as part of the internet.

Abstract: Parallel Processing Communication Accelerator (PPCA) systems and methods for enhancing performance of a Parallel Processing Environment (PPE). In an embodiment, a Message Passing Interface (MPI) devolver enabled PPCA is in communication with the PPE and a host node. The host node executes at least a parallel processing application and an MPI process. The MPI devolver communicates with the MPI process and the PPE to improve the performance of the PPE by offloading MPI process functionality to the PPCA. Offloading MPI processing to the PPCA frees the host node for other processing tasks, for example, executing the parallel processing application, thereby improving the performance of the PPE.

Abstract: A method for interconnecting multiple computational devices in a parallel computing network including a plurality of serially associated pairs of nodes, wherein each of the pairs of nodes is interconnected via at least one physical communication channel. A sufficient virtual channel rate required to provide a predetermined amount of Amdahl scaling is first determined. The maximum number of virtual channels, each having a transmission rate at least equal to the sufficient virtual channel rate, that can be implemented over each physical communication channel is then determined. The physical communication channel between each of the nodes is then subdivided into the determined maximum number of virtual channels.

Abstract: A method using for performing a scatter-type data distribution among a cluster of computational devices. A number of nodes (equal to a value Cg, the number of tree generator channels) are initially generated, each connected to an initial generator, to create respective initial root nodes of an initial tree structure. Data is transmitted from the initial generator to each of the initial root nodes. Cg root nodes, each connected to a respective new generator, are generated to create respective roots of Cg newly generated tree structures. Each of the tree structures is expanded by generating Ct (the number of communication channels per node in each tree structure) new nodes connected to each node generated in each previous step. Data is then transmitted to each of the new nodes from an immediately preceding one of the nodes, and from each new generator to an associated root node.

Abstract: Methods and systems are provided for accelerating execution of programs of the type run by individuals or companies. The methods include the steps of communicating at least one program function to a library in data communication with the program and transmitting the function to a computing facility, typically in the form of computer clusters. The function is processed at the computing facility and results are relayed back to the user of the programs. Users of the invention pay for accelerated execution by one of several interfaces, such as through on-line transactions and/or through prearranged ISP connectivity. Accelerated processing is initiated, typically, by clicking on a computer icon; and results appear seamlessly—though accelerated—to the user. The clusters of the invention can mix and match computers of different processing speeds to maximize the MIPS per dollar in processing accelerated functions for users.