Patents by Inventor Kevin Devey

Kevin Devey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240015067
    Abstract: A computing apparatus, including: a hardware platform; and an interworking broker function (IBF) hosted on the hardware platform, the IBF including a translation driver (TD) associated with a legacy network appliance lacking native interoperability with an orchestrator, the IBF configured to: receive from the orchestrator a network function provisioning or configuration command for the legacy network appliance; operate the TD to translate the command to a format consumable by the legacy network appliance; and forward the command to the legacy network appliance.
    Type: Application
    Filed: September 19, 2023
    Publication date: January 11, 2024
    Applicant: Intel Corporation
    Inventors: John J. Browne, Timothy Verrall, Maryam Tahhan, Michael J. McGrath, Sean Harte, Kevin Devey, Jonathan Kenny, Christopher MacNamara
  • Patent number: 11847008
    Abstract: Technologies for providing efficient detection of idle poll loops include a compute device. The compute device has a compute engine that includes a plurality of cores and a memory. The compute engine is to determine a ratio of unsuccessful operations to successful operations over a predefined time period of a core of the plurality cores that is assigned to continually poll, within the predefined time period, a memory address for a change in status and determine whether the determined ratio satisfies a reference ratio of unsuccessful operations to successful operations. The reference ratio is indicative of a change in the operation of the assigned core. The compute engine is further to selectively increase or decrease a power usage of the assigned core as a function of whether the determined ratio satisfies the reference ratio. Other embodiments are also described and claimed.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: December 19, 2023
    Assignee: Intel Corporation
    Inventors: David Hunt, Niall Power, Kevin Devey, Changzheng Wei, Bruce Richardson, Eliezer Tamir, Andrew Cunningham, Chris MacNamara, Nemanja Marjanovic, Rory Sexton, John Browne
  • Patent number: 11818008
    Abstract: A computing apparatus, including: a hardware platform; and an interworking broker function (IBF) hosted on the hardware platform, the IBF including a translation driver (TD) associated with a legacy network appliance lacking native interoperability with an orchestrator, the IBF configured to: receive from the orchestrator a network function provisioning or configuration command for the legacy network appliance; operate the TD to translate the command to a format consumable by the legacy network appliance; and forward the command to the legacy network appliance.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: November 14, 2023
    Assignee: Intel Corporation
    Inventors: John J. Browne, Timothy Verrall, Maryam Tahhan, Michael J. McGrath, Sean Harte, Kevin Devey, Jonathan Kenny, Christopher MacNamara
  • Publication number: 20230013499
    Abstract: A computing apparatus, including: a hardware platform; and an interworking broker function (IBF) hosted on the hardware platform, the IBF including a translation driver (TD) associated with a legacy network appliance lacking native interoperability with an orchestrator, the IBF configured to: receive from the orchestrator a network function provisioning or configuration command for the legacy network appliance; operate the TD to translate the command to a format consumable by the legacy network appliance; and forward the command to the legacy network appliance.
    Type: Application
    Filed: September 15, 2022
    Publication date: January 19, 2023
    Applicant: Intel Corporation
    Inventors: John J. Browne, Timothy Verrall, Maryam Tahhan, Michael J. McGrath, Sean Harte, Kevin Devey, Jonathan Kenny, Christopher MacNamara
  • Patent number: 11469953
    Abstract: A computing apparatus, including: a hardware platform; and an interworking broker function (IBF) hosted on the hardware platform, the IBF including a translation driver (TD) associated with a legacy network appliance lacking native interoperability with an orchestrator, the IBF configured to: receive from the orchestrator a network function provisioning or configuration command for the legacy network appliance; operate the TD to translate the command to a format consumable by the legacy network appliance; and forward the command to the legacy network appliance.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: October 11, 2022
    Assignee: Intel Corporation
    Inventors: John J. Browne, Timothy Verrall, Maryam Tahhan, Michael J. McGrath, Sean Harte, Kevin Devey, Jonathan Kenny, Christopher MacNamara
  • Patent number: 10657056
    Abstract: Technologies for demoting cache lines to a shared cache include a compute device with at least one processor having multiple cores, a cache memory with a core-local cache and a shared cache, and a cache line demote device. A processor core of a processor of the compute device is configured to retrieve at least a portion of data of a received network packet and move the data into one or more core-local cache lines of the core-local cache. The processor core is further configured to perform a processing operation on the data and transmit a cache line demotion command to the cache line demote device subsequent to having completed the processing operation. The cache line demote device is configured to perform a cache line demotion operation to demote the data from the core-local cache lines to shared cache lines of the shared cache. Other embodiments are described herein.
    Type: Grant
    Filed: June 30, 2018
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: Eliezer Tamir, Bruce Richardson, Niall Power, Andrew Cunningham, David Hunt, Kevin Devey, Changzheng Wei
  • Patent number: 10445272
    Abstract: A network system includes a central processing unit and a peripheral device in electrical communication with the central processing unit. The peripheral device has at least one power input and a data input. The network system also includes an out of band controller in electrical communication with the central processing unit, the peripheral device, and an external management interface. Responsive to an identified threat, the out of band controller is configured to disable the at least one power input and the data input to the peripheral device, where the disablement indicates to the central processing unit that a hot plug event has occurred with respect to the peripheral device. The out of band controller is also configured to enable auxiliary power to the peripheral device such that the out of band controller remains in communication with the peripheral device during remediation of the identified threat.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventors: Kevin Devey, John Browne, Chris Macnamara, Eoin Walsh, Bruce Richardson, Andrew Cunningham, Niall Power, David Hunt, Changzheng Wei, Eliezer Tamir
  • Publication number: 20190097889
    Abstract: A computing apparatus, including: a hardware platform; and an interworking broker function (IBF) hosted on the hardware platform, the IBF including a translation driver (TD) associated with a legacy network appliance lacking native interoperability with an orchestrator, the IBF configured to: receive from the orchestrator a network function provisioning or configuration command for the legacy network appliance; operate the TD to translate the command to a format consumable by the legacy network appliance; and forward the command to the legacy network appliance.
    Type: Application
    Filed: September 27, 2017
    Publication date: March 28, 2019
    Applicant: Intel Corporation
    Inventors: John J. Browne, Timothy Verrall, Maryam Tahhan, Michael J. McGrath, Sean Harte, Kevin Devey, Jonathan Kenny, Christopher MacNamara
  • Publication number: 20190042506
    Abstract: A network system includes a central processing unit and a peripheral device in electrical communication with the central processing unit. The peripheral device has at least one power input and a data input. The network system also includes an out of band controller in electrical communication with the central processing unit, the peripheral device, and an external management interface. Responsive to an identified threat, the out of band controller is configured to disable the at least one power input and the data input to the peripheral device, where the disablement indicates to the central processing unit that a hot plug event has occurred with respect to the peripheral device. The out of band controller is also configured to enable auxiliary power to the peripheral device such that the out of band controller remains in communication with the peripheral device during remediation of the identified threat.
    Type: Application
    Filed: July 5, 2018
    Publication date: February 7, 2019
    Inventors: Kevin Devey, John Browne, Chris Macnamara, Eoin Walsh, Bruce Richardson, Andrew Cunningham, Niall Power, David Hunt, Changzheng Wei, Eliezer Tamir
  • Publication number: 20190041957
    Abstract: Technologies for providing efficient detection of idle poll loops include a compute device. The compute device has a compute engine that includes a plurality of cores and a memory. The compute engine is to determine a ratio of unsuccessful operations to successful operations over a predefined time period of a core of the plurality cores that is assigned to continually poll, within the predefined time period, a memory address for a change in status and determine whether the determined ratio satisfies a reference ratio of unsuccessful operations to successful operations. The reference ratio is indicative of a change in the operation of the assigned core. The compute engine is further to selectively increase or decrease a power usage of the assigned core as a function of whether the determined ratio satisfies the reference ratio. Other embodiments are also described and claimed.
    Type: Application
    Filed: April 12, 2018
    Publication date: February 7, 2019
    Inventors: David Hunt, Niall Power, Kevin Devey, Changzheng Wei, Bruce Richardson, Eliezer Tamir, Andrew Cunningham, Chris MacNamara, Nemanja Marjanovic, Rory Sexton, John Browne
  • Publication number: 20190042419
    Abstract: Technologies for demoting cache lines to a shared cache include a compute device with at least one processor having multiple cores, a cache memory with a core-local cache and a shared cache, and a cache line demote device. A processor core of a processor of the compute device is configured to retrieve at least a portion of data of a received network packet and move the data into one or more core-local cache lines of the core-local cache. The processor core is further configured to perform a processing operation on the data and transmit a cache line demotion command to the cache line demote device subsequent to having completed the processing operation. The cache line demote device is configured to perform a cache line demotion operation to demote the data from the core-local cache lines to shared cache lines of the shared cache. Other embodiments are described herein.
    Type: Application
    Filed: June 30, 2018
    Publication date: February 7, 2019
    Inventors: Eliezer Tamir, Bruce Richardson, Niall Power, Andrew Cunningham, David Hunt, Kevin Devey, Changzheng Wei
  • Publication number: 20190034372
    Abstract: Techniques are provided for multiple device Peripheral Component Interface Express (PCIe) card having a single slot connector and each device interfaces with the single slot connector using distinct, unshared, data lane terminals of the single slot connector. In an example, a PCIe card can include a first device mounted to a circuit board and a second device mounted to the circuit board. The first device can be connected to a first plurality of data lane terminals of a single slot connector of the circuit board. The second device can be connected to a second plurality of data lane terminals of the single slot connector. The first plurality of data lane terminals can be distinct from the second plurality of data lane terminals.
    Type: Application
    Filed: December 15, 2017
    Publication date: January 31, 2019
    Inventors: Dirk Blevins, Kevin Devey, Todd Cameron Langley