Abstract: Structures including a waveguide core and methods of fabricating a structure including a waveguide core. The structure comprises a photonics chip including a first chip region, a second chip region, a first waveguide core in the first chip region, and a second waveguide core in the second chip region. The first chip region adjoins the second chip region along a boundary. The first waveguide core includes a first tapered section, and the second waveguide core includes a second tapered section positioned across the boundary from the first tapered section. The first tapered section has a first width dimension that increases with increasing distance from the boundary, and the second tapered section has a second width dimension that increases with increasing distance from the boundary.

Abstract: Structures including a waveguide core and methods of fabricating a structure including a waveguide core. The structure comprises a photonics chip including a first chip region, a second chip region, a first waveguide core in the first chip region, and a second waveguide core in the second chip region. The first chip region adjoins the second chip region along a boundary. The first waveguide core includes a first tapered section, and the second waveguide core includes a second tapered section positioned across the boundary from the first tapered section. The first tapered section has a first width dimension that increases with increasing distance from the boundary, and the second tapered section has a second width dimension that increases with increasing distance from the boundary.

Abstract: Methods of forming a self-aligned, selective semiconductor on insulator (SOI) structure and a related structure are disclosed. In one embodiment, a method includes providing a substrate; forming a gate structure over a channel within the substrate; recessing a portion of the substrate adjacent the channel; forming an insulating layer on a bottom of the recessed portion; and forming a semiconductor material above the insulating layer. An upper surface of the semiconductor material may be sloped. A MOSFET structure may include a substrate; a channel; a source region and a drain region adjacent the channel; a gate structure above the channel and the substrate; a shallow trench isolation (STI) distal from the gate structure; a selectively laid insulating layer in at least one of the source region and the drain region; and an epitaxially grown semiconductor material above the selectively laid insulating layer.

Abstract: An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.