Abstract: A system and method for forming an embedded chip package is disclosed. The embedded chip package includes a first chip portion having a plurality of pre-patterned re-distribution layers joined together to form a pre-patterned lamination stack, with the pre-patterned lamination stack having a die opening extending therethrough. The embedded chip package also includes a die positioned in the die opening and a second chip portion having at least one uncut re-distribution layer, with the second chip portion affixed to each of the first chip portion and the die and being patterned to be electrically connected to both of the first chip portion and the die.

Abstract: A system and method for forming a wafer level package (WLP) (i.e., wafer level chip size package) is disclosed. The WLP includes a silicon integrated circuit (IC) substrate having a plurality of die pads formed on a top surface thereof and a plurality of polymer laminates positioned thereon. Each of the polymer laminates is comprised of a separate pre-formed laminate sheet and has a plurality of vias formed therein that correspond to a respective die pad. A plurality of metal interconnects are formed on each of the plurality of polymer laminates so as to cover a portion of a top surface of a polymer laminate and extend down through the via and into contact with a metal interconnect on a neighboring polymer laminate positioned below. An input/output (I/O) system interconnect is positioned on a top surface of the wafer level package and is attached to the plurality of metal interconnects.

Abstract: A system and method for forming an embedded chip package is disclosed. The embedded chip package includes a first chip portion having a plurality of pre-patterned re-distribution layers joined together to form a pre-patterned lamination stack, with the pre-patterned lamination stack having a die opening extending therethrough. The embedded chip package also includes a die positioned in the die opening and a second chip portion having at least one uncut re-distribution layer, with the second chip portion affixed to each of the first chip portion and the die and being patterned to be electrically connected to both of the first chip portion and the die.

Abstract: A system and method for forming a wafer level package (WLP) (i.e., wafer level chip size package) is disclosed. The WLP includes a silicon integrated circuit (IC) substrate having a plurality of die pads formed on a top surface thereof and a plurality of polymer laminates positioned thereon. Each of the polymer laminates is comprised of a separate pre-formed laminate sheet and has a plurality of vias formed therein that correspond to a respective die pad. A plurality of metal interconnects are formed on each of the plurality of polymer laminates so as to cover a portion of a top surface of a polymer laminate and extend down through the via and into contact with a metal interconnect on a neighboring polymer laminate positioned below. An input/output (I/O) system interconnect is positioned on a top surface of the wafer level package and is attached to the plurality of metal interconnects.

Abstract: An electronic system (1) having an interconnect structure (30, 45). In one embodiment a system (1) includes a first electronic device (2) with a first plurality of contact pads (15) each having a noble metal (18) formed along a first surface (19), and a second electronic device (3) with a second plurality of contact pads (29) each having a noble metal (18) formed along a first surface (19). The noble metal (18) of one of the contact pads (15) of the first device (2) is bonded to the noble metal (18) of one of the contact pads (29) of the second device (3). In one embodiment of an associated method of forming an interconnect structure (45), a first electronic device (2) is provided with a first plurality of contact pads (15) each having a noble metal (18) along a first surface (19), and a second electronic device (3) is provided with a plurality of contact pads (29) each having a noble metal (18) along a first surface (19).

Abstract: Disclosed is a biaxially oriented multilayer film comprising at least two layers A-B, wherein A and B represent separate layers at least one of which layers comprises a polyimide having a Tg of greater than about 200° C., wherein the film has a CTE of less than 35 ppm/° C., and wherein A comprises 60 wt. %-100 wt. % of amorphous polymer with 0 wt. %-40 wt. % of crystallizable polymer, and B comprises 60 wt. %-100 wt. % crystallizable polymer with 0 wt. %-40 wt. % amorphous polymer, the relative thicknesses of layer A to layer B are in a ratio in a range of between 1:5 and 1:100, and the thickness of the film is in a range of between 5 ?m and 125 ?m. Also disclosed is a biaxially oriented monolithic film comprising a polyimide with structural units formally derived from 3,4-diaminodiphenylether and 4,4-oxydiphthalic anhydride. Laminates comprising the films and methods for making film and laminate are also disclosed. Articles comprising a film or laminate of the invention are also disclosed.

Abstract: A method for fabricating an interconnect comprising providing a carrier substrate, wherein the carrier substrate comprises a plurality of interconnect traces and a plurality of input/output contacts; providing a flexible substrate having a first side and a second side, disposing the second side of the sacrificial layer onto the first side of the flexible substrate to form a first assembly, disposing the carrier substrate onto the first assembly; and removing the sacrificial layer and the carrier substrate to form the interconnect.

Abstract: A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor.

Abstract: A method of making an electronic device cooling system includes forming a thermally conductive layer on an inner surface of the substrate and laser ablating the thermally conductive layer to form microchannels.

Abstract: A method for making an interconnect is provided. The method includes depositing a conductive layer on a substrate, depositing a protective layer on the conductive layer, patterning the protective layer to form openings to the conductive layer, depositing contact pads on the conductive layer through the openings in the protective layer, the contact pads comprising a conductive material, and patterning the conductive layer and the protective layer to form electrical traces on the substrate.

Abstract: A method of processing a semiconductor substrate is provided. The method includes depositing an amorphous hydrogenated carbon film on a semiconductor substrate using a low temperature plasma deposition process and performing at least one high temperature processing step on the semiconductor substrate. The SiC substrate is processed by ion implanting at least one dopant species into at least one selected region of the SiC substrate, depositing a amorphous hydrogenated carbon film on the SiC substrate using a plasma enhanced chemical vapor deposition (PECVD) process, performing at least one high temperature processing step on the SiC substrate and removing the amorphous hydrogenated carbon film after performing the high temperature processing step.

Abstract: A method for fabricating an interconnect comprising providing a carrier substrate, wherein the carrier substrate comprises a plurality of interconnect traces and a plurality of input/output contacts; providing a flexible substrate having a first side and a second side, disposing the second side of the sacrificial layer onto the first side of the flexible substrate to form a first assembly, disposing the carrier substrate onto the first assembly; and removing the sacrificial layer and the carrier substrate to form the interconnect. A detector for use in an imaging system comprises the aforementioned interconnect.

Abstract: An electronic assembly having at least a heat dissipating unit and a heat generating unit is provided. At least one of the heat dissipating unit and the heat generating unit has at least one deliberately modified surface.