Abstract: An apparatus includes a host and a baseboard management controller. The baseboard management controller includes a semiconductor package; and the semiconductor package includes a memory, a security hardware processor; and a main hardware processor. The main hardware processor causes the baseboard management controller to serve as an agent that, independently from the host, responds to communications with a remote management entity to manage the host. The security hardware processor manages the storage of a secret of the host in the memory.

Abstract: A method for assembling a computing device including initiating a board management controller of the computing device, the board management controller having at least one fuse, forming data to control a video display operatively connected to the computing device to show an image of a watermark, and modifying the computing device. The method also includes blowing the at least one fuse in response to modifying the computing device and adjusting the watermark in response to blowing the at least one fuse.

Abstract: A method for assembling a computing device including initiating a board management controller of the computing device, the board management controller having at least one fuse, forming data to control a video display operatively connected to the computing device to show an image of a watermark, and modifying the computing device. The method also includes blowing the at least one fuse in response to modifying the computing device and adjusting the watermark in response to blowing the at least one fuse.

Abstract: Emulating devices across selected communication pathways by way of a terminal session. At least some of the illustrative embodiments are methods including establishing a terminal session between a first computer system and a second computer system (the second computer system distinct from the first computer system, and the second computer system having a management processor with a plurality of communication pathways to a main processor of the second computer system), configuring the management processor to send data regarding emulation of a first mass storage device across a first selected pathway of the plurality of communication pathways to the main processor (the configuring by way of the terminal session), and emulating (by the management processor) the first mass storage device across the first selected pathway.

Abstract: Emulating devices across selected communication pathways by way of a terminal session. At least some of the illustrative embodiments are methods including establishing a terminal session between a first computer system and a second computer system (the second computer system distinct from the first computer system, and the second computer system having a management processor with a plurality of communication pathways to a main processor of the second computer system), configuring the management processor to send data regarding emulation of a first mass storage device across a first selected pathway of the plurality of communication pathways to the main processor (the configuring by way of the terminal session), and emulating (by the management processor) the first mass storage device across the first selected pathway.

Abstract: An electronic device includes a panel having a display screen that moves along a first axis and pivots about a second axis perpendicular to the first axis.

Abstract: A fault detection system includes a fault indicator and power monitors coupled to the fault indicator. The fault indicator is configured to indicate a fault for a first one of the power monitors which detects a corresponding voltage is not between a corresponding maximum value and a corresponding minimum value.

Abstract: Embodiments of the present invention provide a system for analysis of an inter-integrated circuit router. The inter-integrated circuit router comprises an internal bus comprising a plurality of debug lines, a plurality of bus ports wherein at least one bus port comprises a bus port analysis line, and a control logic comprising a control logic analysis line. The inter-integrated circuit router further comprises a debug connector coupled to said debug lines, said bus port analysis line and said control logic analysis line.