Abstract: A storage system includes a controller connected to a solid state memory device. The controller releases the physical address for reassignment when no pending reads are associated with the physical address. In certain embodiments, a read status table may be included within the storage system. In certain embodiments, subsequent to the release of the physical address, erase operations may erase data at the physical address and the physical address may be reassigned to a new logical address by ensuing host write operations.

Abstract: A storage system includes a memory controller connected to a solid state memory device and a read status table that tracks a pending read from the solid state memory device and a physical address of the solid state memory device that is associated with the pending read. The memory controller releases the physical address for reassignment when the read status table indicates that no pending reads are associated with the physical address. In certain embodiments, the read status table may be included within the memory controller. In certain embodiments, subsequent to the release of the physical address, erase operations may erase data at the physical address and the physical address may be reassigned to a new logical address by ensuing host write operations.

Abstract: A storage system includes a memory controller connected to a solid state memory device and a read status table that tracks a pending read from the solid state memory device and a physical address of the solid state memory device that is associated with the pending read. The memory controller releases the physical address for reassignment when the read status table indicates that no pending reads are associated with the physical address. In certain embodiments, the read status table may be included within the memory controller. In certain embodiments, subsequent to the release of the physical address, erase operations may erase data at the physical address and the physical address may be reassigned to a new logical address by ensuing host write operations.

Abstract: A storage system includes a memory controller connected to a solid state memory device and a read status table that tracks a pending read from the solid state memory device and a physical address of the solid state memory device that is associated with the pending read. The memory controller releases the physical address for reassignment when the read status table indicates that no pending reads are associated with the physical address. In certain embodiments, the read status table may be included within the memory controller. In certain embodiments, subsequent to the release of the physical address, erase operations may erase data at the physical address and the physical address may be reassigned to a new logical address by ensuing host write operations.

Abstract: A storage system includes a memory controller connected to a solid state memory device and a read status table that tracks a pending read from the solid state memory device and a physical address of the solid state memory device that is associated with the pending read. The memory controller releases the physical address for reassignment when the read status table indicates that no pending reads are associated with the physical address. In certain embodiments, the read status table may be included within the memory controller. In certain embodiments, subsequent to the release of the physical address, erase operations may erase data at the physical address and the physical address may be reassigned to a new logical address by ensuing host write operations.

Abstract: A storage system includes a memory controller connected to a solid state memory device and a read status table that tracks a pending read from the solid state memory device and a physical address of the solid state memory device that is associated with the pending read. The memory controller releases the physical address for reassignment when the read status table indicates that no pending reads are associated with the physical address. In certain embodiments, the read status table may be included within the memory controller. In certain embodiments, subsequent to the release of the physical address, erase operations may erase data at the physical address and the physical address may be reassigned to a new logical address by ensuing host write operations.

Abstract: According to one embodiment, a method includes issuing a read request to read one or more units of data from at least one non-volatile random access memory (NVRAM) device. The read request includes one or more read voltage thresholds. The method also includes receiving the one or more data units and read command parameters used to read the one or more data units from the at least one NVRAM device. Moreover, the method includes storing error-free data units, the read command parameters used to read the error-free data units from the at least one NVRAM device, and a read completion status to one of a plurality of read buffers. The read completion status indicates a completed read when a data unit is error-free and indicates an incomplete read when a data unit is errored.

Abstract: According to one embodiment, a system includes a read buffer memory configured to store data to support integrated XOR reconstructed data and read-retry data and logic configured to receive data units and read command parameters used to read the data units from a non-volatile random access memory (NVRAM) device, determine which read buffers from the read buffer memory to store the data units, determine an error status for each of the data units, wherein the error status indicates whether each data unit includes errored data or error-free data, store each error-free data unit and the read command parameters to a corresponding read buffer, reject each errored data unit without affecting a corresponding read buffer, and retry to read only errored data units from the NVRAM device until each of the data units is stored in the read buffer memory.

Abstract: According to one embodiment, a system includes a read butter memory configured to store data to support integrated XOR reconstructed data and read-retry data and logic configured to receive data units and read command parameters used to read the data units from a non-volatile random access memory (NVRAM) device, determine which read buffers from the read buffer memory to store the data units, determine an error status for each of the data units, wherein the error status indicates whether each data unit includes errored data or error-free data, store each error-free data unit and the read command parameters to a corresponding read buffer, reject each errored data unit without affecting a corresponding read buffer, and retry to read only errored data units from the NVRAM device until each of the data units is stored in the read buffer memory.

Abstract: A storage system includes a memory controller connected to a solid state memory device and a read status table that tracks a pending read from the solid state memory device and a physical address of the solid state memory device that is associated with the pending read. The memory controller releases the physical address for reassignment when the read status table indicates that no pending reads are associated with the physical address. In certain embodiments, the read status table may be included within the memory controller. In certain embodiments, subsequent to the release of the physical address, erase operations may erase data at the physical address and the physical address may be reassigned to a new logical address by ensuing host write operations.

Abstract: A method of calculating a diagonal interleaved parity word for groups of words sampled from a bus is provided, wherein a predetermined number of words are included in each sampling cycle. The bus carries successive data words that are followed by a control word. At each sampling cycle, diagonal XOR calculations chains are propagated through the words that were sampled. However, if a sampling cycle includes the control word, the words following the control word are assigned to logical zero values. The diagonal XOR calculation chains may then be terminated after processing the words in this sampling cycle to derive an intermediate diagonal parity word. The intermediate diagonal parity word may then be adjusted according to the number of words that were assigned logical zero values to calculate a second diagonal interleaved parity word.

Abstract: A method of calculating a diagonal interleaved parity word for groups of words sampled from a bus is provided, wherein a predetermined number of words are included in each sampling cycle. The bus carries successive data words that are followed by a control word. At each sampling cycle, diagonal XOR calculations chains are propagated through the words that were sampled. However, if a sampling cycle includes the control word, the words following the control word are assigned to logical zero values. The diagonal XOR calculation chains may then be terminated after processing the words in this sampling cycle to derive an intermediate diagonal parity word. The intermediate diagonal parity word may then be adjusted according to the number of words that were assigned logical zero values to calculate the diagonal interleaved parity word.

Abstract: A programmable logic device is programmed to implement a finite state machine that may sequence through a plurality of states in a single clock cycle of the programmable logic device. The programmable logic device includes a plurality of programmable blocks programmed to instantiate memories. Each memory is programmed to determine a next state of the finite state machine based upon a current state of the finite state machine and current input conditions for the finite state machine.