Abstract: An imaging device includes a controller, a power supply, a regulator, and a switch. The controller is configured to control an imaging unit, on the basis of a command and data that are received from a host in accordance with an I2C/I3C communication protocol. The power supply is configured to supply a voltage to a digital block of the controller. The digital block is configured to be subjected to dynamic voltage frequency scaling within one-frame operation. The regulator and the switch are provided between the digital block and the power supply, and coupled in parallel with each other.

Abstract: A low-dropout regulator architecture with undershoot mitigation. In one embodiment, a system including a low-dropout regulator and a digital-to-analog converter (DAC). The low-dropout regulator is configured to generate a load current and output a voltage at an output node. The digital-to-analog converter (DAC) is configured to receive a control input, and output a DAC current to the low-dropout regulator based on the control input. The DAC current is configured to modify the load current and mitigate an undershoot of the voltage that is output at the output node while the voltage transitions from a high voltage level to a low voltage level.

Abstract: An image sensor includes a pixel array including a plurality of pixels each including a photosensitive element, and a readout circuit, wherein the pixels are arranged in at least two columns, within each column at least some of the pixels of the column are connected with a common column bus, respectively, for each column the readout circuit includes a first analog-to-digital converter (ADC) and a second ADC, for each column the first ADC is connected with the column bus, and for each column the second ADC is connectable with at least one of the column bus and a reference potential or the second ADC is connected with one optically shielded pixel of the pixel array.

Abstract: An imaging device includes a controller, a power supply, a regulator, and a switch. The controller is configured to control an imaging unit, on the basis of a command and data that are received from a host in accordance with an I2C/I3C communication protocol. The power supply is configured to supply a voltage to a digital block of the controller. The digital block is configured to be subjected to dynamic voltage frequency scaling within one-frame operation. The regulator and the switch are provided between the digital block and the power supply, and coupled in parallel with each other.

Abstract: An imaging pixel (2) to mitigate cross-talk effects comprises a voltage supply node (VN) to receive a supply voltage (VDD), and an output node (ON) to provide a pixel output signal. The imaging pixel (2) further comprises a photosensitive element (10), and a source follower transistor (31) having a control node coupled to the photosensitive element (10). The source follower transistor (31) is interposed between the voltage supply node (VN) and the output node (ON). The imaging pixel (2) comprises a clamping circuit (20) being interposed between the voltage supply node (VN) and the output node (ON).

Abstract: Oscillator circuits, electronic devices, and methods are disclosed. In one embodiment, an oscillator circuit includes a plurality of oscillator transistors comprising a plurality of gates, a plurality of adjustment transistors coupled to the plurality of gates, a differential output coupled to the plurality of oscillator transistors, a plurality of current transistors configured to receive one or more mixed bias current outputs, and generate a main current based on the one or more mixed bias current outputs, the one or more mixed bias current outputs and the main current being substantially constant over a range of temperatures, and one or more switches configured to set an oscillation frequency of the differential output by driving a first portion of a main current through at least one of the plurality of oscillator transistors, and driving a second portion of the main current through at least one of the plurality of adjustment transistors.

Abstract: A low-dropout regulator architecture with undershoot mitigation. In one embodiment, a system including a low-dropout regulator and a digital-to-analog converter (DAC). The low-dropout regulator is configured to generate a load current and output a voltage at an output node. The digital-to-analog converter (DAC) is configured to receive a control input, and output a DAC current to the low-dropout regulator based on the control input. The DAC current is configured to modify the load current and mitigate an undershoot of the voltage that is output at the output node while the voltage transitions from a high voltage level to a low voltage level.

Abstract: A system includes: a power supply; an adaptively biased power event detection comparator; and an adaptive bias circuit for the adaptively biased power event detection comparator. The adaptively biased power event detection comparator is configured to compare a first input corresponding to a voltage level of the power supply with a second input corresponding to a reference voltage. The adaptive bias circuit is configured to increase a bias current for the adaptively biased power event detection comparator based on the voltage level of the power supply decreasing to be closer to the reference voltage.

Abstract: An input device associated with a sensing region is provided. The input device includes: a sensor electrode configured to receive a resulting signal associated with the sensing region; an auxiliary component configured to generate an output based on a differential current; a mixer circuit coupled to the sensor electrode and including: a current conveyor configured to generate a replica of the resulting signal; and a switch array, in series with the replica and the differential current, and configured to generate the differential current by demodulating the replica of the resulting signal.

Abstract: An oscillator circuit is disclosed. The oscillator circuit includes: oscillator transistors including gates; adjustment transistors coupled to the gates; a differential output coupled to the oscillator transistors; a switch configured to set an oscillation frequency of the differential output by driving: a first current including a first portion of a main current through at least one of the oscillator transistors; and a second current including a second portion of the main current through at least one of the adjustment transistors; a first set of auxiliary current sources configured to adjust a temperature coefficient of the oscillator circuit by driving a first set of auxiliary currents through the oscillator transistors; and a second set of auxiliary current sources configured to maintain the oscillation frequency of the differential output by driving, in response to driving the first set of auxiliary currents, a second set of auxiliary currents though the adjustment transistors.

Abstract: A system includes: a power supply; an adaptively biased power event detection comparator; and an adaptive bias circuit for the adaptively biased power event detection comparator. The adaptively biased power event detection comparator is configured to compare a first input corresponding to a voltage level of the power supply with a second input corresponding to a reference voltage. The adaptive bias circuit is configured to increase a bias current for the adaptively biased power event detection comparator based on the voltage level of the power supply decreasing to be closer to the reference voltage.

Abstract: An input device associated with a sensing region is disclosed. The input device includes: a sensor electrode configured to receive a resulting signal associated with the sensing region; a current conveyor configured to generate a first replica of the resulting signal; a mixer circuit configured to generate a differential current by demodulating the first replica of the resulting signal; an interference detection circuit (IDC) configured to: generate a second replica of the resulting signal based on the first replica; determine the second replica includes an interference signal based on a reference current; and generate an interference alert signal in response to determining the second replica includes the interference signal; and an auxiliary component configured to generate an output based on the differential current and the interference alert signal.

Abstract: An oscillator circuit is disclosed. The oscillator circuit includes: oscillator transistors including gates; adjustment transistors coupled to the gates; a differential output coupled to the oscillator transistors; a switch configured to set an oscillation frequency of the differential output by driving: a first current including a first portion of a main current through at least one of the oscillator transistors; and a second current including a second portion of the main current through at least one of the adjustment transistors; a first set of auxiliary current sources configured to adjust a temperature coefficient of the oscillator circuit by driving a first set of auxiliary currents through the oscillator transistors; and a second set of auxiliary current sources configured to maintain the oscillation frequency of the differential output by driving, in response to driving the first set of auxiliary currents, a second set of auxiliary currents though the adjustment transistors.

Abstract: An input device associated with a sensing region is provided. The input device includes: a sensor electrode configured to receive a resulting signal associated with the sensing region; an auxiliary component configured to generate an output based on a differential current; a mixer circuit coupled to the sensor electrode and including: a current conveyor configured to generate a replica of the resulting signal; and a switch array, in series with the replica and the differential current, and configured to generate the differential current by demodulating the replica of the resulting signal.

Abstract: In a current-mode bandgap reference integrated circuit: a bandgap voltage generator is configured to generate a bandgap voltage, a zero-temperature coefficient current generator configured to generate a zero-temperature coefficient current, and a proportional to absolute temperature current generator configured to generate a proportional to absolute temperature current. The integrated circuit includes a first pair of bipolar junction transistors (BJT) comprising a first BJT and a second BJT. The integrated circuit also includes a second pair of bipolar junction transistors, comprising a third BJT and a fourth BJT. The first pair of BJTs matches the second pair of BJTs.

Abstract: An apparatus, system, and method are disclosed for compensating input offset of an amplifier having first and second amplifier output nodes. The method comprises generating a proportional-to-absolute temperature (PTAT) current, generating a complementary-to-absolute temperature (CTAT) current, and selecting, based on the input offset, one of the first and second amplifier output nodes into which a compensation current is to be coupled. The compensation current is based on a selected one of the PTAT current and CTAT current.

Abstract: An apparatus, system, and method are disclosed for compensating input offset of an amplifier having first and second amplifier output nodes. The method comprises generating a proportional-to-absolute temperature (PTAT) current, generating a complementary-to-absolute temperature (CTAT) current, and selecting, based on the input offset, one of the first and second amplifier output nodes into which a compensation current is to be coupled. The compensation current is based on a selected one of the PTAT current and CTAT current.

Abstract: In a current-mode bandgap reference integrated circuit: a bandgap voltage generator is configured to generate a bandgap voltage, a zero-temperature coefficient current generator configured to generate a zero-temperature coefficient current, and a proportional to absolute temperature current generator configured to generate a proportional to absolute temperature current. The integrated circuit includes a first pair of bipolar junction transistors (BJT) comprising a first BJT and a second BJT. The integrated circuit also includes a second pair of bipolar junction transistors, comprising a third BJT and a fourth BJT. The first pair of BJTs matches the second pair of BJTs.