Patents by Inventor Kevin J. Haley

Kevin J. Haley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7132313
    Abstract: A semiconductor chip is shown containing an integral heat spreading layer that more effectively transmits heat from the die to ambient as a result of spreading the heat out on the die over a larger cross sectional area. Local hot spots are minimized which allows the semiconductor chip to operate at a higher frequency for a given upper threshold temperature. Also shown is a method of manufacturing such a semiconductor chip, and the associated method of cooling a semiconductor chip.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: November 7, 2006
    Assignee: Intel Corporation
    Inventors: Michael O'Connor, Kevin J. Haley, Biswajit Sur
  • Publication number: 20040104014
    Abstract: A semiconductor chip is shown containing an integral heat spreading layer that more effectively transmits heat from the die to ambient as a result of spreading the heat out on the die over a larger cross sectional area. Local hot spots are minimized which allows the semiconductor chip to operate at a higher frequency for a given upper threshold temperature. Also shown is a method of manufacturing such a semiconductor chip, and the associated method of cooling a semiconductor chip.
    Type: Application
    Filed: November 25, 2003
    Publication date: June 3, 2004
    Applicant: Intel Corporation.
    Inventors: Michael O'Connor, Kevin J. Haley, Biswajit Sur
  • Patent number: 6667548
    Abstract: A semiconductor chip is shown containing an integral heat spreading layer that more effectively transmits heat from the die to ambient as a result of spreading the heat out on the die over a larger cross sectional area. Local hot spots are minimized which allows the semiconductor chip to operate at a higher frequency for a given upper threshold temperature. Also shown is a method of manufacturing such a semiconductor chip, and the associated method of cooling a semiconductor chip.
    Type: Grant
    Filed: April 6, 2001
    Date of Patent: December 23, 2003
    Assignee: Intel Corporation
    Inventors: Michael O'Connor, Kevin J. Haley, Biswajit Sur
  • Publication number: 20020145194
    Abstract: A semiconductor chip is shown containing an integral heat spreading layer that more effectively transmits heat from the die to ambient as a result of spreading the heat out on the die over a larger cross sectional area. Local hot spots are minimized which allows the semiconductor chip to operate at a higher frequency for a given upper threshold temperature. Also shown is a method of manufacturing such a semiconductor chip, and the associated method of cooling a semiconductor chip.
    Type: Application
    Filed: April 6, 2001
    Publication date: October 10, 2002
    Applicant: Intel Corporation
    Inventors: Michael O'Connor, Kevin J. Haley, Biswajit Sur
  • Patent number: 6404047
    Abstract: Socketable balls are mounted to a BGA package by first placing the balls into pockets or holes of a tray that are sized such that when the balls are inserted, an upper portion of the ball protrudes above a planar surface of the tray. A layer of a polymer material is then applied over the balls and a top area of each of the balls is exposed, and plated with solder. During the plating step the polymer provides a solder-tight seal against each of the balls such that, except for the top area, the rest of the surface area of the balls remains solder-free. The solder-plated top area of each of the balls is then bonded to the corresponding plurality of lands of the package by reflowing the solder to establish electrical contact therebetween.
    Type: Grant
    Filed: August 11, 2000
    Date of Patent: June 11, 2002
    Assignee: Intel Corporation
    Inventors: Kevin J. Haley, Larry Moresco
  • Publication number: 20010040788
    Abstract: A heat exchanger. A first heat transfer element has an end which forms an engaging surface. A second heat transfer element has a receptacle portion which is integrally formed and has an engaging surface that is urged against the engaging surface of the first heat transfer element when the first heat transfer element and the second heat transfer element are mated.
    Type: Application
    Filed: September 30, 1998
    Publication date: November 15, 2001
    Inventors: MICHAEL O'CONNOR, KEVIN J. HALEY
  • Patent number: 6313987
    Abstract: A heat exchanger adapated for heat dissipation. A first heat transfer element has an end which forms an engaging surface. A second heat transfer element has a receptacle portion which is integrally formed and has an engaging surface that is urged against the engaging surface of the first heat transfer element when the first heat transfer element and the second heat transfer element are mated.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: November 6, 2001
    Assignee: Intel Corporation
    Inventors: Michael O'Connor, Kevin J. Haley
  • Patent number: 6168976
    Abstract: Socketable balls are mounted to a BGA package by first placing the balls into pockets or holes of a tray that are sized such that when the balls are inserted, an upper portion of the ball protrudes above a planar surface of the tray. A layer of a polymer material is then applied over the balls and a top area of each of the balls is exposed, and plated with solder. During the plating step the polymer provides a solder-tight seal against each of the balls such that, except for the top area, the rest of the surface area of the balls remains solder-free. The solder-plated top area of each of the balls is then bonded to the corresponding plurality of lands of the package by reflowing the solder to establish electrical contact therebetween.
    Type: Grant
    Filed: January 6, 1999
    Date of Patent: January 2, 2001
    Assignee: Intel Corporation
    Inventors: Kevin J. Haley, Larry Moresco
  • Patent number: 6043560
    Abstract: A method and apparatus for controlling the thickness of a thermal interface between a processor die and a thermal plate in a microprocessor assembly are provided. The apparatus includes a generally rectangular shaped thermal top cover having a recessed portion of predetermined depth and aperture therein. The thermal top cover fits over the processor die. A thermal interface layer fills the recessed portion of the thermal top cover covering the processor die. The depth of the recessed portion is greater than the thickness of the processor die so that the thickness of the thermal interface layer is controlled. A thermal plate is placed over the thermal top cover in contact with the thermal grease so as to form a thermal path from the processor die to the thermal plate.
    Type: Grant
    Filed: December 3, 1997
    Date of Patent: March 28, 2000
    Assignee: Intel Corporation
    Inventors: Kevin J. Haley, Niel C. Delaplane, Ravindranath V. Mahajan, Robert Starkston, Charles A. Gealer, Joseph C. Krauskopf
  • Patent number: 5359768
    Abstract: A very small integrated circuit package. The package of the present invention includes a substrate or die coupled to a heatsink. The substrate or die has solder bumps for being directly mounted to a circuit board. The heatsink is coupled to the die before the die is mounted to the circuit board. The heatsink is mounted using adhesive. By mounting the heatsink before the die is mounted, the heatsink may be used to handle of the substrate or die during the manufacturing and testing process, thereby increasing the reliability of the die by increased protection.
    Type: Grant
    Filed: July 16, 1993
    Date of Patent: November 1, 1994
    Assignee: Intel Corporation
    Inventor: Kevin J. Haley
  • Patent number: 5359225
    Abstract: A high leadcount surface mount IC package. The IC package of the present invention includes a plastic molded compound which is localized over the surface of the die, such that it covers the interconnections of the die. The package includes a leadframe having many leads. The leads are supported using a ring support structure.
    Type: Grant
    Filed: November 6, 1992
    Date of Patent: October 25, 1994
    Assignee: Intel Corporation
    Inventor: Kevin J. Haley
  • Patent number: 5290735
    Abstract: A high leadcount surface mount IC package. The IC package of the present invention includes a plastic molded compound which is localized over the surface of the die, such that it covers the interconnections of the die. The package includes a leadframe having many leads. The leads are supported using a ring support structure.
    Type: Grant
    Filed: February 1, 1993
    Date of Patent: March 1, 1994
    Assignee: Intel Corporation
    Inventor: Kevin J. Haley