Patents by Inventor Kevin J. Kranzusch

Kevin J. Kranzusch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10310879
    Abstract: An embodiment of the invention sets forth a primary processing unit, a secondary processing unit coupled to the primary processing unit and accessible via a plurality of channels and a plurality of guest virtual machines executing on the primary processing unit. Each guest virtual machine includes a driver associated with the secondary processing unit, and a privileged virtual machine executing on the primary processing unit and configured to allocate a different set of channels of the plurality of channels to each of the drivers included in the guest virtual machines, where a first set of channels allocated to a first driver enables the first driver to access the secondary processing unit without conflicting with any of the other and with minimal performance overhead by directly accessing the secondary processing unit channels.
    Type: Grant
    Filed: October 10, 2011
    Date of Patent: June 4, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: William J. Earl, Kevin J. Kranzusch, Satya Kiran Popuri, Christopher W. Johnson
  • Publication number: 20130091500
    Abstract: An embodiment of the invention sets forth a primary processing unit, a secondary processing unit coupled to the primary processing unit and accessible via a plurality of channels and a plurality of guest virtual machines executing on the primary processing unit. Each guest virtual machine includes a driver associated with the secondary processing unit, and a privileged virtual machine executing on the primary processing unit and configured to allocate a different set of channels of the plurality of channels to each of the drivers included in the guest virtual machines, where a first set of channels allocated to a first driver enables the first driver to access the secondary processing unit without conflicting with any of the other and with minimal performance overhead by directly accessing the secondary processing unit channels.
    Type: Application
    Filed: October 10, 2011
    Publication date: April 11, 2013
    Inventors: William J. Earl, Kevin J. Kranzusch, Satya Kiran Popuri, Christopher W. Johnson
  • Patent number: 7903116
    Abstract: A graphics system adapts a performance level to be sufficient to maintain a performance criterion in an acceptable range. In one embodiment, at least one utilization parameter of the core clock domain and the memory clock domain is monitored. In response to detecting an over-utilization condition, the performance level is increased to maintain the desired minimum number of frames per second. In response to detecting an under-utilization condition, the performance level is decreased to reduce power consumption and increase the lifetime of the graphics system.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: March 8, 2011
    Assignee: Nvidia Corporation
    Inventors: Michael M. Klock, Paul V. Puey, Paul E. Van Der Kouwe, Jeffrey M. Smith, Kevin J. Kranzusch
  • Patent number: 7802147
    Abstract: Method and apparatus for channel monitoring, channel throughput restoration and system testing in relation to channel monitoring and channel throughput restoration is described. A failure status of a channel is identified. The channel and at least one engine associated with the failure status is disabled. A client application assigned such a channel is notified that the channel has been disabled. The at least one engine and the channel associated with the failure status is restored. Additionally, the client application is allowed to destroy and reconstruct command status and state of the channel. Additionally, error information for the failure status is stored. Other aspects include: error injection which may be used for testing ability to detect an error and recover; and a graphical user interface for rendering mode selection for increasing channel throughput.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: September 21, 2010
    Assignee: NVIDIA Corporation
    Inventors: Christopher W. Johnson, Kevin J. Kranzusch, Andrew Sobczyk
  • Patent number: 7627787
    Abstract: Method and apparatus for channel monitoring, channel throughput restoration and system testing in relation to channel monitoring and channel throughput restoration is described. A failure status of a channel is identified. The channel and at least one engine associated with the failure status is disabled. A client application assigned such a channel is notified that the channel has been disabled. The at least one engine and the channel associated with the failure status is restored. Additionally, the client application is allowed to destroy and reconstruct command status and state of the channel. Additionally, error information for the failure status is stored. Other aspects include: error injection which may be used for testing ability to detect an error and recover; and a graphical user interface for rendering mode selection for increasing channel throughput.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: December 1, 2009
    Assignee: NVIDIA Corporation
    Inventors: Christopher W. Johnson, Kevin J. Kranzusch, Andrew Sobczyk
  • Patent number: 7535433
    Abstract: A system and method for modifying the configuration of one or more graphics adapters and one or more displays without rebooting the system allows a user to quickly transition between different graphics adapter/display configurations. A single display driver interfaces between the operating system and the one or more graphics devices. The display driver reconfigures the one or more graphics devices to change the adapter/display configuration without shutting down or rebooting the system. Unlike a conventional system reboot performed by the operating system, the display driver checks that there are no memory leaks or error conditions during the reconfiguration.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: May 19, 2009
    Assignee: NVIDIA Corporation
    Inventors: Herbert O. Ledebohm, Todd Michael Poynter, Shail Dave, Mark A. Einkauf, Kevin J. Kranzusch
  • Patent number: 7444551
    Abstract: Method and apparatus for channel monitoring, channel throughput restoration and system testing in relation to channel monitoring and channel throughput restoration is described. A failure status of a channel is identified. The channel and at least one engine associated with the failure status is disabled. A client application assigned such a channel is notified that the channel has been disabled. The at least one engine and the channel associated with the failure status is restored. Additionally, the client application is allowed to destroy and reconstruct command status and state of the channel. Additionally, error information for the failure status is stored. Other aspects include: error injection which may be used for testing ability to detect an error and recover; and a graphical user interface for rendering mode selection for increasing channel throughput.
    Type: Grant
    Filed: December 16, 2002
    Date of Patent: October 28, 2008
    Assignee: NVIDIA Corporation
    Inventors: Christopher W. Johnson, Kevin J. Kranzusch, Andrew Sobczyk
  • Patent number: 7382366
    Abstract: Overclocking parameters in a graphics system are automatically set. In one embodiment, in response to a user request, overclocking parameters for different sets of overclocking parameters are tested using a graphical stress test to select optimum overclocking parameters.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: June 3, 2008
    Assignee: NVIDIA Corporation
    Inventors: Michael M. Klock, Jeffrey M. Smith, Satish D. Salian, Kevin J. Kranzusch
  • Publication number: 20080028181
    Abstract: Circuits, methods, and apparatus that reduce or eliminate system memory accesses to retrieve address translation information. In one example, these accesses are reduced or eliminated by pre-populating a graphics TLB with entries that are used to translate virtual addresses used by a GPU to physical addresses used by a system memory. Translation information is maintained by locking or restricting entries in the graphics TLB that are needed for display access. This may be done by limiting access to certain locations in the graphics TLB, by storing flags or other identifying information in the graphics TLB, or by other appropriate methods. In another example, memory space is allocated by a system BIOS for a GPU, which stores a base address and address range. Virtual addresses in the address range are translated by adding them to the base address.
    Type: Application
    Filed: March 21, 2007
    Publication date: January 31, 2008
    Applicant: NVIDIA Corporation
    Inventors: Peter C. Tong, Sonny S. Yeoh, Kevin J. Kranzusch, Gary D. Lorensen, Kaymann L. Woo, Ashish Kishen Kaul, Colyn S. Case, Stefan A. Gottschalk, Dennis K. Ma
  • Publication number: 20070268296
    Abstract: A system and method for modifying the configuration of one or more graphics adapters and one or more displays without rebooting the system allows a user to quickly transition between different graphics adapter/display configurations. A single display driver interfaces between the operating system and the one or more graphics devices. The display driver reconfigures the one or more graphics devices to change the adapter/display configuration without shutting down or rebooting the system. Unlike a conventional system reboot performed by the operating system, the display driver checks that there are no memory leaks or error conditions during the reconfiguration.
    Type: Application
    Filed: May 18, 2006
    Publication date: November 22, 2007
    Inventors: Herbert O. Ledebohm, Todd Michael Poynter, Shail Dave, Mark A. Einkauf, Kevin J. Kranzusch