Patents by Inventor Kevin J. Lee

Kevin J. Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8994174
    Abstract: A structure and method of handling a device wafer during through-silicon via (TSV) processing are described in which a device wafer is bonded to a temporary support substrate with a permanent thermosetting material. Upon removal of the temporary support substrate a planar frontside bonding surface including a reflowed solder bump and the permanent thermosetting material is exposed.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: March 31, 2015
    Assignee: Intel Corporation
    Inventor: Kevin J. Lee
  • Patent number: 8933564
    Abstract: Embodiments of the present disclosure describe techniques and configurations associated with forming a landing structure for a through-silicon via (TSV) using interconnect structures of interconnect layers. In eon embodiment, an apparatus includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a device layer disposed on the first surface of the semiconductor substrate, the device layer including one or more transistor devices, interconnect layers disposed on the device layer, the interconnect layers including a plurality of interconnect structures and one or more through-silicon vias disposed between the first surface and the second surface, wherein the plurality of interconnect structures include interconnect structures that are electrically coupled with the one or more TSVs and configured to provide one or more corresponding landing structures of the one or more TSVs. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: January 13, 2015
    Assignee: Intel Corporation
    Inventors: Christopher M. Pelto, Ruth A. Brain, Kevin J. Lee, Gerald S. Leatherman
  • Patent number: 8910927
    Abstract: An archery bow holding device that is preferably mounted to a ball joint assembly for attachment to a table top, bench or like surface, and provides a movable mount for the archery bow holding device that holds an archery bow for performing work thereon. The preferred ball joint assembly includes a cylindrical housing that is slotted on opposite sides thereof from a center opening in the housing top and contains a ball that mounts a stem that the archery bow holding device is secured to, with the stem fitted through a slot through the housing top, to tilt between the slots and pivot when the ball in unlocked and, with the ball locked, provides a rigid mount to the archery bow holding device that includes a main beam that is bent to provide a rest for an archery bow limb positioned and clamped there against for an operator to work on.
    Type: Grant
    Filed: September 16, 2012
    Date of Patent: December 16, 2014
    Assignee: Berry's Manufacturing, Inc.
    Inventors: Kevin J. Lee, Tony James Berry
  • Publication number: 20140264679
    Abstract: An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) with an upper MTJ layer, lower MTJ layer, and tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. In an embodiment the first and second ILDs directly contact one another. Other embodiments are described herein.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Kevin J. Lee, Tahir Ghani, Joseph M. Steigerwald, John H. Epple, Yih Wang
  • Publication number: 20140264668
    Abstract: An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Kevin J. Lee, Tahir Ghani, Joseph M. Steigerwald, John H. Epple, Yih Wang
  • Publication number: 20140175651
    Abstract: Embodiments of the present disclosure describe techniques and configurations associated with forming a landing structure for a through-silicon via (TSV) using interconnect structures of interconnect layers. In eon embodiment, an apparatus includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a device layer disposed on the first surface of the semiconductor substrate, the device layer including one or more transistor devices, interconnect layers disposed on the device layer, the interconnect layers including a plurality of interconnect structures and one or more through-silicon vias disposed between the first surface and the second surface, wherein the plurality of interconnect structures include interconnect structures that are electrically coupled with the one or more TSVs and configured to provide one or more corresponding landing structures of the one or more TSVs. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Inventors: Christopher M. Pelto, Ruth A. Brain, Kevin J. Lee, Gerald S. Leatherman
  • Patent number: 8704336
    Abstract: Selective removal of on-die redistribution interconnect material from a scribe-line region is generally described. In one example, an apparatus includes a first semiconductor die having a redistribution layer comprising redistribution dielectric and one or more redistribution metal interconnects, a second semiconductor die coupled with the first semiconductor die, the second semiconductor die having a redistribution layer comprising redistribution dielectric and one or more redistribution metal interconnects, and a scribe-line region disposed between the first semiconductor die and second semiconductor die, the scribe-line region having a majority or substantially all of redistribution dielectric or redistribution metal, or suitable combinations thereof, selectively removed to enable die singulation through the scribe-line region.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: April 22, 2014
    Assignee: Intel Corporation
    Inventors: Jun He, Kevin J. Lee, Subhash Joshi
  • Publication number: 20140077432
    Abstract: An archery bow holding device that is preferably mounted to a ball joint assembly for attachment to a table top, bench or like surface, and provides a movable mount for the archery bow holding device that holds an archery bow for performing work thereon. The preferred ball joint assembly includes a cylindrical housing that is slotted on opposite sides thereof from a center opening in the housing top and contains a ball that mounts a stem that the archery bow holding device is secured to, with the stem fitted through a slot through the housing top, to tilt between the slots and pivot when the ball in unlocked and, with the ball locked, provides a rigid mount to the archery bow holding device that includes a main beam that is bent to provide a rest for an archery bow limb positioned and clamped there against for an operator to work on.
    Type: Application
    Filed: September 16, 2012
    Publication date: March 20, 2014
    Inventors: Kevin J. Lee, Tony James Berry
  • Publication number: 20130285257
    Abstract: A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow.
    Type: Application
    Filed: October 28, 2011
    Publication date: October 31, 2013
    Inventors: Kevin J. Lee, Mark T. Bohr, Andrew W. Yeoh, Christopher M. Pelto, Hiten Kothari, Seshu V. Sattiraju, Hang-Shing Ma
  • Publication number: 20130264707
    Abstract: A structure and method of handling a device wafer during through-silicon via (TSV) processing are described in which a device wafer is bonded to a temporary support substrate with a permanent thermosetting material. Upon removal of the temporary support substrate a planar frontside bonding surface including a reflowed solder bump and the permanent thermosetting material is exposed.
    Type: Application
    Filed: September 30, 2011
    Publication date: October 10, 2013
    Inventor: Kevin J. Lee
  • Publication number: 20130256910
    Abstract: A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a single damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.
    Type: Application
    Filed: October 28, 2011
    Publication date: October 3, 2013
    Inventors: Kevin J. Lee, Mark T. Bohr, Andrew W. Yeoh, Christopher M. Pelto, Hiten Kothari, Seshu V. Sattiraju, Hang-Shing Ma
  • Patent number: 8297605
    Abstract: A ball joint assembly that is a movable mount for a work holding device for holding an item, such as a rifle or pistol, where the ball joint assembly is for seating on, or mounting onto, a table top, bench, or like surface. The ball joint assembly includes a cylindrical housing slotted on opposite sides thereof from a center opening in the housing top and contains a ball that rests on a plunger top end of a jacking screw that is turned in a round nut by a lever arm, and the ball joint assembly is fitted into the housing. Turning of the lever arm that is fitted through a housing lateral slot extends the plunger top into the ball, lifting the ball to lock it against a housing top concave surface, and which ball includes a stem extending through the housing top to tilt between the slots and pivot when the ball in unlocked, and the ball stem end includes a tool mounting for connection to the work holding devices.
    Type: Grant
    Filed: November 2, 2009
    Date of Patent: October 30, 2012
    Assignee: Berry's Manufacturing, Inc.
    Inventors: Kevin J. Lee, Tony James Berry
  • Publication number: 20120077706
    Abstract: The invention relates to a method for determining if a test compound, or a mix of compounds, modulates the interaction between two proteins of interest. The determination is made possible via the use of two recombinant molecules, one of which contains the first protein a cleavage site for a proteolytic molecules, and an activator of a gene. The second recombinant molecule includes the second protein and the proteolytic molecule. If the test compound binds to the first protein, a reaction is initiated whereby the activator is cleaved, and activates a reporter gene.
    Type: Application
    Filed: August 18, 2011
    Publication date: March 29, 2012
    Applicant: Life Technologies Corporation
    Inventors: Kevin J. LEE, Richard Axel, Walter Strapps, Gilad Barnea
  • Publication number: 20120068342
    Abstract: The present disclosure relates to the field of fabricating microelectronic devices, wherein a conductive adhesive is used as a temporary microelectronic wafer bonding adhesive to prevent damage to microelectronic devices resulting from electrical charge build-up on the microelectronic devices during the formation of through-silicon vias.
    Type: Application
    Filed: September 16, 2010
    Publication date: March 22, 2012
    Inventor: Kevin J. Lee
  • Patent number: 8104172
    Abstract: Embodiments of buffer coatings for semiconductor and integrated circuit manufacturing are presented herein.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: January 31, 2012
    Assignee: Intel Corporation
    Inventors: Michael D. Goodner, Kevin J. Lee
  • Patent number: 8017398
    Abstract: The invention relates to a method for determining if a test compound, or a mix of compounds, modulates the interaction between two proteins of interest. The determination is made possible via the use of two recombinant molecules, one of which contains the first protein a cleavage site for a proteolytic molecules, and an activator of a gene. The second recombinant molecule includes the second protein and the proteolytic molecule. If the test compound binds to the first protein, a reaction is initiated whereby the activator is cleaved, and activates a reporter gene.
    Type: Grant
    Filed: February 2, 2006
    Date of Patent: September 13, 2011
    Assignees: Life Technologies Corporation, The Trustees of Columbia University in the City of New York
    Inventors: Kevin J. Lee, Richard Axel, Walter Strapps, Gilad Barnea
  • Patent number: 7982311
    Abstract: An apparatus comprises a semiconductor substrate having a device layer, a plurality of metallization layers, a passivation layer, and a metal bump formed on the passivation layer that is electrically coupled to at least one of the metallization layers. The apparatus further includes a solder limiting layer formed on the passivation layer that masks an outer edge of the top surface of the metal bump, thereby making the outer edge of the top surface non-wettable to a solder material.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: July 19, 2011
    Assignee: Intel Corporation
    Inventor: Kevin J. Lee
  • Patent number: 7964965
    Abstract: Embodiments of an apparatus and methods for forming thick metal interconnect structures for integrated structures are generally described herein. Other embodiments may be described and claimed.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: June 21, 2011
    Assignee: Intel Corporation
    Inventor: Kevin J. Lee
  • Publication number: 20110101192
    Abstract: A ball joint assembly and work holding device where the ball joint assembly provides a movable mount for different work holding devices that each provide for holding an item, such as a fire arm, archery bow and/or the like, where the ball joint assembly is for seating on, or mounting onto, a table top, bench, or like surface. The ball joint assembly includes a cylindrical housing slotted on opposite sides thereof from a center opening in the housing top and contains a ball that rests on a plunger top end of a jacking screw that is turned in a round nut by a lever arm, and the ball joint assembly is fitted into the housing.
    Type: Application
    Filed: November 2, 2009
    Publication date: May 5, 2011
    Inventors: Kevin J. Lee, Tony James Berry
  • Patent number: 7833899
    Abstract: A multi-layer thick metallization structure for a microelectronic device includes a first barrier layer (111), a first metal layer (112) over the first barrier layer, a first passivation layer (113) over the first metal layer, a via structure (114) extending through the first passivation layer, a second barrier layer (115) over the first passivation layer and in the via structure, a second metal layer (116) over the second barrier layer, and a second passivation layer (117) over the second metal layer and the first passivation layer.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: November 16, 2010
    Assignee: Intel Corporation
    Inventor: Kevin J. Lee