Patents by Inventor Kevin J. Ryan

Kevin J. Ryan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240139493
    Abstract: Provided herein is a disinfecting device including a container containing a chlorhexidine-based solution having a chlorhexidine concentration of from 0.2-2.0% wt/vol. Provided also is a medical connector disinfected with the disinfecting device. A method of disinfecting a medical connector using the disinfecting device is also disclosed.
    Type: Application
    Filed: November 2, 2022
    Publication date: May 2, 2024
    Inventors: Kevin M. Ryan, Andrew Woodbridge Van Cott, Richard Bradley Timmers, Shoshana San Solo, Shishir Prasad, Narasinha C. Parasnis, Anurag Mathur, Chang Jiang, Kelsey Ann Graves, Joseph J. Dajcs, Qin Chen
  • Publication number: 20240069759
    Abstract: Methods, systems, and devices for triple activate command row address latching are described. For instance, a memory device may receive a first activate command that indicates a first set of bits of a row address, a second activate command that indicates a second set of bits of the row address, and a third activate command that indicates a third set of bits of the row address. The memory device may activate a page of memory based on receiving the first activate command, the second activate command, and the third activate command, where the page of memory is addressed according to the first set of bits, the second set of bits, and the third set of bits.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Kwang-Ho Cho, Miki Matsumoto, Kevin J. Ryan
  • Patent number: 11853552
    Abstract: The hybrid memory device may include volatile and non-volatile memory cells on a single substrate, or die. The non-volatile memory cells may have ferroelectric capacitors and the volatile memory cells may have paraelectric or linear dielectric capacitors for their respective logic storage components. In some examples, the volatile memory cells may be used as a cache for the non-volatile memory cells. Or the non-volatile memory cells may be used as a back-up for the volatile memory cells. By placing both types of cells on a single die, rather than separate dies, various performance metrics may be improved, including those related to power consumption and operation speed.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: December 26, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kevin J. Ryan, Kirk D. Prall, Durai Vishak Nirmal Ramaswamy, Robert Quinn
  • Publication number: 20230282544
    Abstract: This application relates to modifications and enhancements to assemblies used with integrated circuits. In the described embodiments, multiple thermal components (e.g., vapor chambers, fin stacks, heat pipes) can be used to provide a dual-sided thermal energy extraction solution for a circuit board and an integrated circuit located on the circuit board. The thermal components can provide thermal energy dissipation capabilities for additional heat-generating components on the circuit board. Additionally, multiple plates can provide a compression force used to maintain contact between the integrated circuit and the circuit board, and in particular, between contact pads of the integrated circuit and pins, or springs, of a socket located on the circuit board.
    Type: Application
    Filed: March 4, 2022
    Publication date: September 7, 2023
    Inventors: Simon J. TRIVETT, Brett W. DEGNER, Mahesh S. HARDIKAR, Michael E. LECLERC, Eric R. PRATHER, Kevin J. RYAN
  • Patent number: 11665869
    Abstract: This application relates to display devices and the layout/architecture of various internal components to enhance thermal energy management. A display device described herein may include one or more fan assemblies that drive ambient air into the display device to cool heat-generating components of the display device, and also to drive the ambient air, once heated through convectively cooling the heat-generating components, out of the display device. Further, the location of the heat-generating components is such that the heat-generating components upstream relative to the one or more fan assemblies. In this manner, the ambient air can pass over or through the heat-generating components prior to reaching the one or more fan assemblies. Additionally, heat-generating components, such as a backlit device and a power supply unit, are positioned relatively close to vent inlets in the display device. As a result, these heat-generating devices are immediately cooled with the ambient air.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: May 30, 2023
    Assignee: APPLE INC.
    Inventors: Michael E. Leclerc, Kevin J. Ryan, Brett W. Degner
  • Publication number: 20220354031
    Abstract: This application relates to display devices and the layout/architecture of various internal components to enhance thermal energy management. A display device described herein may include one or more fan assemblies that drive ambient air into the display device to cool heat-generating components of the display device, and also to drive the ambient air, once heated through convectively cooling the heat-generating components, out of the display device. Further, the location of the heat-generating components is such that the heat-generating components upstream relative to the one or more fan assemblies. In this manner, the ambient air can pass over or through the heat-generating components prior to reaching the one or more fan assemblies. Additionally, heat-generating components, such as a backlit device and a power supply unit, are positioned relatively close to vent inlets in the display device. As a result, these heat-generating devices are immediately cooled with the ambient air.
    Type: Application
    Filed: August 10, 2021
    Publication date: November 3, 2022
    Inventors: Michael E. LECLERC, Kevin J. RYAN, Brett W. DEGNER
  • Publication number: 20210405884
    Abstract: Methods, systems, and devices for a hybrid memory device are described. The hybrid memory device may include volatile and non-volatile memory cells on a single substrate, or die. The non-volatile memory cells may have ferroelectric capacitors and the volatile memory cells may have paraelectric or linear dielectric capacitors for their respective logic storage components. In some examples, the volatile memory cells may be used as a cache for the non-volatile memory cells. Or the non-volatile memory cells may be used as a back-up for the volatile memory cells. By placing both types of cells on a single die, rather than separate dies, various performance metrics may be improved, including those related to power consumption and operation speed.
    Type: Application
    Filed: July 13, 2021
    Publication date: December 30, 2021
    Inventors: Kevin J. Ryan, Kirk D. Prall, Durai Vishak Nirmal Ramaswamy, Robert Quinn
  • Patent number: 11193386
    Abstract: A core assembly for fabricating an air cooled engine component for a gas turbine engine includes an end portion for defining passages within a side of an engine component. The end portion defines a first cross-section. A middle portion is spaced apart from the end portion and defines passages through a middle part of the engine component. The middle portion defines a second cross-section. One of the first cross-section and the second cross-section includes a first height greater than a second height. An air cooled engine component for a gas turbine engine and a gas turbine engine are also disclosed.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: December 7, 2021
    Assignee: Raytheon Technologies Corporation
    Inventors: Timothy M. Davis, Paul M. Lutjen, Kevin J. Ryan
  • Patent number: 11068166
    Abstract: A hybrid memory device may include volatile and non-volatile memory cells on a single substrate, or die. The non-volatile memory cells may have ferroelectric capacitors and the volatile memory cells may have paraelectric or linear dielectric capacitors for their respective logic storage components. In some examples, the volatile memory cells may be used as a cache for the non-volatile memory cells. Or the non-volatile memory cells may be used as a back-up for the volatile memory cells. By placing both types of cells on a single die, rather than separate dies, various performance metrics may be improved, including those related to power consumption and operation speed.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: July 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kevin J. Ryan, Kirk D. Prall, Durai Vishak Nirmal Ramaswamy, Robert Quinn
  • Patent number: 10966343
    Abstract: A structure can include a body having a first surface and a second opposing surface. The three-dimensional structure can include the body defining a first pattern of first cavities extending into the body from the first surface and the body defining a second pattern of second cavities extending into the body from the second surface. One or more first cavities can eccentrically intersect with one or more second cavities to define a pattern of apertures in the body.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: March 30, 2021
    Assignee: APPLE INC.
    Inventors: Richard P. Howarth, Nicholas A. Rundle, Bartley K. Andre, Sung-Ho Tan, Lauren M. Farrell, Kevin J. Ryan, David H. Narajowski
  • Patent number: 10790363
    Abstract: The disclosure relates to methods of forming integrated circuit (IC) structures with a metal cap on a cobalt layer for source and drain regions of a transistor. An integrated circuit (IC) structure according to the disclosure may include: a semiconductor fin on a substrate; a gate structure over the substrate, the gate structure having a first portion extending transversely across the semiconductor fin; an insulator cap positioned on the gate structure above the semiconductor fin; a cobalt (Co) layer on the semiconductor fin adjacent to the gate structure, wherein an upper surface of the Co layer is below an upper surface of the gate structure; and a metal cap on the Co layer.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: September 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Laertis Economikos, Kevin J. Ryan, Ruilong Xie, Hui Zang
  • Patent number: 10785845
    Abstract: An electronic device may have a display mounted in a housing. The housing may have a stand that supports the housing on a support surface or may have other shapes. The display may have pixels that display an image. The display may also have a two-dimensional array of light-emitting devices such as light-emitting diodes that supply backlight illumination for the pixels. An array of temperature sensors may be overlapped by the pixels. Control circuitry may maintain historical backlight aging information during operation of the display. The aging information may include information on output brightness levels of the light-emitting diodes and light-emitting diode operating temperatures.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: September 22, 2020
    Assignee: Apple Inc.
    Inventors: Adrian E. Sun, ByoungSuk Kim, Jason P. Marini, Jun Qi, Kerry J. Kopp, Matthew W. Cooper, Mingxia Gu, Yanming Li, Kevin J. Ryan, Shmuel G. Link
  • Publication number: 20200245497
    Abstract: A structure can include a body having a first surface and a second opposing surface. The three-dimensional structure can include the body defining a first pattern of first cavities extending into the body from the first surface and the body defining a second pattern of second cavities extending into the body from the second surface. One or more first cavities can eccentrically intersect with one or more second cavities to define a pattern of apertures in the body.
    Type: Application
    Filed: April 16, 2020
    Publication date: July 30, 2020
    Inventors: Richard P. Howarth, Nicholas A. Rundle, Bartley K. Andre, Sung-Ho Tan, Lauren M. Farrell, Kevin J. Ryan, David H. Narajowski
  • Patent number: 10667426
    Abstract: A structure can include a body having a first surface and a second opposing surface. The three-dimensional structure can include the body defining a first pattern of first cavities extending into the body from the first surface and the body defining a second pattern of second cavities extending into the body from the second surface. One or more first cavities can eccentrically intersect with one or more second cavities to define a pattern of apertures in the body.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: May 26, 2020
    Assignee: APPLE INC.
    Inventors: Richard P. Howarth, Nicholas A. Rundle, Bartley K. Andre, Sung-Ho Tan, Lauren M. Farrell, Kevin J. Ryan, David H. Narajowski
  • Patent number: 10619504
    Abstract: A blade outer air seal includes a body that extends axially between forward and aft rails and circumferentially between lateral faces. The body has an inner arcuate surface that is configured to seal relative to a blade tip. The body includes a plurality of cooling holes that extend through an exterior surface of the body. Each of the plurality of cooling holes break through the exterior surface at geometric coordinates in accordance with Cartesian coordinate values of X, Y and Z as set forth in Tables 1, 2 and 3. Each of the geometric coordinates is measured from a reference point on the body.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: April 14, 2020
    Assignee: United Technologies Corporation
    Inventors: Terence P. Tyler, Thurman Carlo Dabbs, Kevin J. Ryan, Nathan K. Galle
  • Publication number: 20200100387
    Abstract: A structure can include a body having a first surface and a second opposing surface. The three-dimensional structure can include the body defining a first pattern of first cavities extending into the body from the first surface and the body defining a second pattern of second cavities extending into the body from the second surface. One or more first cavities can eccentrically intersect with one or more second cavities to define a pattern of apertures in the body.
    Type: Application
    Filed: May 14, 2019
    Publication date: March 26, 2020
    Inventors: Richard P. Howarth, Nicholas A. Rundle, Bartley K. Andre, Sung-Ho Tan, Lauren M. Farrell, Kevin J. Ryan, David H. Narajowski
  • Publication number: 20200044034
    Abstract: The disclosure relates to methods of forming integrated circuit (IC) structures with a metal cap on a cobalt layer for source and drain regions of a transistor. An integrated circuit (IC) structure according to the disclosure may include: a semiconductor fin on a substrate; a gate structure over the substrate, the gate structure having a first portion extending transversely across the semiconductor fin; an insulator cap positioned on the gate structure above the semiconductor fin; a cobalt (Co) layer on the semiconductor fin adjacent to the gate structure, wherein an upper surface of the Co layer is below an upper surface of the gate structure; and a metal cap on the Co layer.
    Type: Application
    Filed: August 3, 2018
    Publication date: February 6, 2020
    Inventors: Laertis Economikos, Kevin J. Ryan, Ruilong Xie, Hui Zang
  • Publication number: 20190212919
    Abstract: Methods, systems, and devices for a hybrid memory device are described. The hybrid memory device may include volatile and non-volatile memory cells on a single substrate, or die. The non-volatile memory cells may have ferroelectric capacitors and the volatile memory cells may have paraelectric or linear dielectric capacitors for their respective logic storage components. In some examples, the volatile memory cells may be used as a cache for the non-volatile memory cells. Or the non-volatile memory cells may be used as a back-up for the volatile memory cells. By placing both types of cells on a single die, rather than separate dies, various performance metrics may be improved, including those related to power consumption and operation speed.
    Type: Application
    Filed: March 19, 2019
    Publication date: July 11, 2019
    Inventors: Kevin J. Ryan, Kirk D. Prall, Durai Vishak Nirmal Ramaswamy, Robert Quinn
  • Patent number: 10309253
    Abstract: A blade outer air seal for a gas turbine engine includes a gas path surface exposed to exhaust gas flow, a first side extending radially outward from the gas path surface, a second side extending radially outward from the gas path surface, and a plurality of film cooling holes disposed on at least one of the gas path surface. The first side and the second side, the film cooling holes are disposed at locations described by a set of Cartesian coordinates set forth in Table 1. The Cartesian coordinates are provided by an axial coordinate, a circumferential coordinate and a radial coordinate relative to a defined point of origin. A gas turbine engine is also disclosed.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: June 4, 2019
    Assignee: United Technologies Corporation
    Inventors: Kevin J. Ryan, Terence P. Tyler, Jr., Ken F. Blaney
  • Patent number: 10282108
    Abstract: The hybrid memory device may include volatile and non-volatile memory cells on a single substrate, or die. The non-volatile memory cells may have ferroelectric capacitors and the volatile memory cells may have paraelectric or linear dielectric capacitors for their respective logic storage components. In some examples, the volatile memory cells may be used as a cache for the non-volatile memory cells. Or the non-volatile memory cells may be used as a back-up for the volatile memory cells. By placing both types of cells on a single die, rather than separate dies, various performance metrics may be improved, including those related to power consumption and operation speed.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: May 7, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kevin J. Ryan, Kirk D. Prall, Durai Vishak Nirmal Ramaswamy, Robert Quinn