Abstract: There is disclosed a call announcement circuit arranged for connection to a communication system via a voice (or data) path and also via a separate control channel. Using this arrangement, the system main processor can control the message delivery capacity of the announcement circuit since the circuit has direct access to the internal system buses. This configuration allows detailed control of the announcement circuit on channels separate from the communication channel.

Abstract: In many situations, contiguous data is not stored at contiguous locations within a memory. This fact alone causes an increase in processor time for retrieval purposes or the intervention of a memory management unit of some type. The situation is compounded when large amounts of data must be obtained from the memory or stored in the memory in real time. This problem is addressed by arranging a dual ported memory between the main memory and the processor and transferring the desired data into the dual ported memory. A pair of buffers are then used for each channel having access to the memory. While one buffer is being read, the other is being loaded. This structure also allows multiple devices to access the single main memory substantially simultaneously.

Abstract: There is disclosed a call announcement circuit integrated into the switching network of a PBX switching system such that the announcement board resides in one of the port slots and has direct access to the internal system buses. The circuit can handle many separate announcements each stored at a selectable compression ratio. Each such announcement can be recorded or played in any of the time slots under processor control. This configuration allows tradeoffs between storage capacity and compression ratio (i.e., speech clarity) and also allows messages to be played on any line or to any station via the communication bus and the selected time slot.

Abstract: There is disclosed a control channel interface circuit for interfacing a port processor of a distributed multiprocessor communication system to a common time division multiplexed bus. The detection, extraction and synchronization of control messages passed between a central processor and port processor via a TDM bus are handled by the interface unit thereby relieving a port processor of this burden. A group of control time slots within a system frame are dedicated for the transfer of control messages between port processors and a central processor. The interface unit also monitors the operability of a respective port processor and automatically disables a faulty processor.