Patents by Inventor Kevin Lin
Kevin Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11830768Abstract: Integrated circuit (IC) interconnect lines having line breaks and line bridges within one interconnect level that are based on a single lithographic mask pattern. Multi-patterning may be employed to define a grating structure of a desired pitch in a first mask layer. Breaks and bridges between the grating structures may be derived from a second mask layer through a process-based selective occlusion of openings defined in the second mask layer that are below a threshold minimum lateral width. Portions of the grating structure underlying openings defined in the second mask layer that exceed the threshold minimum lateral width are removed. Trenches in an underlayer may then be etched based on a union of the remainder of the grating structure and the occluded openings in the second mask layer. The trenches may then be backfilled to form the interconnect lines.Type: GrantFiled: November 19, 2021Date of Patent: November 28, 2023Assignee: Intel CorporationInventors: Kevin Lin, Christopher J. Jezewski
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Publication number: 20230352598Abstract: An integrated circuit includes: a gate dielectric; a first layer adjacent to the gate dielectric; a second layer adjacent to the first layer, the second layer comprising an amorphous material; a third layer adjacent to the second layer, the third layer comprising a crystalline material; and a source or drain at least partially adjacent to the third layer. In some cases, the crystalline material of the third layer is a first crystalline material, and the first layer comprises a second crystalline material, which may be the same as or different from the first crystalline material. In some cases, the gate dielectric includes a high-K dielectric material. In some cases, the gate dielectric, the first layer, the second layer, the third layer, and the source or drain are part of a back-gate transistor structure (e.g., back-gate TFT), which may be part of a memory structure (e.g., located within an interconnect structure).Type: ApplicationFiled: June 30, 2023Publication date: November 2, 2023Applicant: Intel CorporationInventors: Van H. Le, Abhishek A. Sharma, Gilbert Dewey, Kent Millard, Jack Kavalieros, Shriram Shivaraman, Tristan A. Tronic, Sanaz Gardner, Justin R. Weber, Tahir Ghani, Li Huey Tan, Kevin Lin
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Patent number: 11798838Abstract: Embodiments herein describe techniques for a semiconductor device including a carrier wafer, and an integrated circuit (IC) formed on a device wafer bonded to the carrier wafer. The IC includes a front end layer having one or more transistors at front end of the device wafer, and a back end layer having a metal interconnect coupled to the one or more transistors. One or more gaps may be formed by removing components of the one or more transistors. Furthermore, the IC includes a capping layer at backside of the device wafer next to the front end layer of the device wafer, filling at least partially the one or more gaps of the front end layer. Moreover, the IC includes one or more air gaps formed within the one or more gaps, and between the capping layer and the back end layer. Other embodiments may be described and/or claimed.Type: GrantFiled: March 19, 2019Date of Patent: October 24, 2023Assignee: Intel CorporationInventors: Ehren Mannebach, Aaron Lilak, Rishabh Mehandru, Hui Jae Yoo, Patrick Morrow, Kevin Lin
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Patent number: 11764306Abstract: Described is an apparatus which comprises: a gate comprising a metal; a first layer adjacent to the gate, the first layer comprising a dielectric material; a second layer adjacent to the first layer, the second layer comprising a second material; a third layer adjacent to the second layer, the third layer comprising a third material including an amorphous metal oxide; a fourth layer adjacent to the third layer, the fourth layer comprising a fourth material, wherein the fourth and second materials are different than the third material; a source partially adjacent to the fourth layer; and a drain partially adjacent to the fourth layer.Type: GrantFiled: September 13, 2021Date of Patent: September 19, 2023Assignee: Intel CorporationInventors: Van H. Le, Abhishek A. Sharma, Gilbert Dewey, Kent Millard, Jack Kavalieros, Shriram Shivaraman, Tristan A. Tronic, Sanaz Gardner, Justin R. Weber, Tahir Ghani, Li Huey Tan, Kevin Lin
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Patent number: 11715791Abstract: A semiconductor-on-insulator (SOI) substrate with a compliant substrate layer advantageous for seeding an epitaxial III-N semiconductor stack upon which III-N devices (e.g., III-N HFETs) may be formed. The compliant layer may be (111) silicon, for example. The SOI substrate may further include another layer that may have one or more of lower electrical resistivity, greater thickness, or a different crystal orientation relative to the compliant substrate layer. A SOI substrate may include a (100) silicon layer advantageous for integrating Group IV devices (e.g., Si FETs), for example. To reduce parasitic coupling between an HFET and a substrate layer of relatively low electrical resistivity, one or more layers of the substrate may be removed within a region below the HFETs. Once removed, the resulting void may be backfilled with another material, or the void may be sealed, for example during back-end-of-line processing.Type: GrantFiled: September 28, 2017Date of Patent: August 1, 2023Assignee: Intel CorporationInventors: Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta, Kevin Lin, Paul Fischer
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Patent number: 11710636Abstract: Metal spacer-based approaches for fabricating conductive lines/interconnects are described. In an example, an integrated circuit structure includes a substrate. A first spacer pattern is on the substrate, the first spacer pattern comprising a first plurality of dielectric spacers and a first plurality of metal spacers formed along sidewalls of the first plurality of dielectric spacers, wherein the first plurality of dielectric spacers have a first width (W1). A second spacer pattern is on the substrate, where the second spacer pattern interleaved with the first spacer pattern, the second spacer pattern comprising a second plurality of dielectric spacers having a second width (W2) formed on exposed sidewalls of the first plurality of metal spacers, and a second plurality of metal spacers formed on exposed sidewalls of the second plurality of dielectric spacers.Type: GrantFiled: June 20, 2018Date of Patent: July 25, 2023Assignee: Intel CorporationInventors: Kevin Lin, Charles Wallace
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Patent number: 11705395Abstract: An integrated circuit structure comprises a first and second conductive structures formed in an interlayer dielectric (ILD) of a metallization stack over a substrate. The first conductive structure comprises a first conductive line, and first dummy structures located adjacent to one or more sides of the first conductive line, wherein the first dummy structures comprise respective arrays of dielectric core segments having a Young's modulus larger than the Young's modulus of the ILD, the dielectric core segments being approximately 1-3 microns in width and spaced apart by approximately 1-3 microns. The second conductive structure formed in the ILD comprises a conductive surface and second dummy structures formed in the conductive surface, where the second dummy structures comprising an array of conductive pillars.Type: GrantFiled: June 25, 2018Date of Patent: July 18, 2023Assignee: Intel CorporationInventor: Kevin Lin
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Patent number: 11664270Abstract: An apparatus is provided which includes: a first stack including a lower, a middle, and an upper layer of conductive material with insulator layers therebetween, and a second stack including the middle and upper layers with one of the insulator layers therebetween. In an example, a first of the insulator layers has a lower breakdown voltage than a second of the insulator layers. The apparatus further includes a first via over the first stack, wherein the first via is in contact with a pair of the lower, middle and upper layers that have the first of the insulator layers therebetween. The apparatus further includes a second via over the second stack, wherein the second via extends through the upper layer and is in contact with the middle layer. In an example, the second via is isolated from a sidewall of the upper layer by a spacer.Type: GrantFiled: April 5, 2021Date of Patent: May 30, 2023Assignee: Intel CorporationInventor: Kevin Lin
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Patent number: 11647511Abstract: There is provided a signalling method for use in an advanced wireless communication network (100) that supports a first duplex mode, a second duplex mode different to the first duplex mode, and carrier aggregation of the first second duplex modes. This method includes configuring a UE (104-106) for data communication with the network (100) through a first access node (101) as a PCell, on the first duplex mode and with a first transmission mode (TM) including one or more transport blocks (TBs). This method also includes configuring the UE (104-106) for data communication with the network (100) through a second access node (103) as a SCell, on the second duplex mode and with a second TM including one or more TBs. The second TM associated with the second access node (103) is configured independently of the first TM associated with the first access node (101).Type: GrantFiled: July 2, 2021Date of Patent: May 9, 2023Assignee: NEC CORPORATIONInventors: Yuanrong Lan, Kevin Lin, Phong Nguyen
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Patent number: 11645506Abstract: A computing system is provided. The computing system includes a processor configured to execute a convolutional neural network that has been trained, the convolutional neural network including a backbone network that is a concatenated pyramid network, a plurality of first head neural networks, and a plurality of second head neural networks. At the backbone network, the processor is configured to receive an input image as input and output feature maps extracted from the input image. The processor is configured to: process the feature maps using each of the first head neural networks to output corresponding keypoint heatmaps; process the feature maps using each of the second head neural networks to output corresponding part affinity field heatmaps; link the keypoints into one or more instances of virtual skeletons using the part affinity fields; and output the instances of the virtual skeletons.Type: GrantFiled: August 24, 2022Date of Patent: May 9, 2023Assignee: Microsoft Technology Licensing, LLCInventors: Lijuan Wang, Kevin Lin, Zicheng Liu, Kun Luo
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Patent number: 11605592Abstract: A multilayer conductive line is disclosed. The multilayer conductive line includes a dielectric layer, a Ta barrier layer on the dielectric layer and a superlattice on the Ta barrier layer. The superlattice includes a plurality of interleaved ferromagnetic and non-ferromagnetic material.Type: GrantFiled: December 26, 2018Date of Patent: March 14, 2023Assignee: Intel CorporationInventors: Noriyuki Sato, Kevin Lin, Kevin O'Brien, Hui Jae Yoo
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Integrated circuits (IC's) with electro-migration (EM)—resistant segments in an interconnect level
Patent number: 11557536Abstract: Integrated circuit (IC) interconnect lines having improved electromigration resistance. Multi-patterning may be employed to define a first mask pattern. The first mask pattern may be backfilled and further patterned based on a second mask layer through a process-based selective occlusion of openings defined in the second mask layer that are below a threshold minimum lateral width. Portions of material underlying openings defined in the second mask layer that exceed the threshold are removed. First trenches in an underlying dielectric material layer may be etched based on a union of the remainder of the first mask layer and the partially occluded second mask layer. The first trenches may then be backfilled with a first conductive material to form first line segments. Additional trenches in the underlayer may then be etched and backfilled with a second conductive material to form second line segments that are coupled together by the first line segments.Type: GrantFiled: December 27, 2017Date of Patent: January 17, 2023Assignee: Intel CorporationInventors: Kevin Lin, Christopher J. Jezewski, Manish Chandhok -
Publication number: 20220405550Abstract: A computing system is provided. The computing system includes a processor configured to execute a convolutional neural network that has been trained, the convolutional neural network including a backbone network that is a concatenated pyramid network, a plurality of first head neural networks, and a plurality of second head neural networks. At the backbone network, the processor is configured to receive an input image as input and output feature maps extracted from the input image. The processor is configured to: process the feature maps using each of the first head neural networks to output corresponding keypoint heatmaps; process the feature maps using each of the second head neural networks to output corresponding part affinity field heatmaps; link the keypoints into one or more instances of virtual skeletons using the part affinity fields; and output the instances of the virtual skeletons.Type: ApplicationFiled: August 24, 2022Publication date: December 22, 2022Applicant: Microsoft Technology Licensing, LLCInventors: Lijuan WANG, Kevin LIN, Zicheng LIU, Kun LUO
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Patent number: 11502031Abstract: An apparatus is provided, which includes a stack of a first plurality of layers interleaved with a second plurality of layers. In an example, the first plurality of layers includes conductive material, and the second plurality of layers includes insulating material. In an example, the first plurality of layers includes an upper layer and lower layer. A first via may extend through at least a portion of the stack, where the first via may be in contact with the upper layer and the lower layer. A second via may extend through at least a portion of the stack, where the second via may be isolated from the upper layer and lower layer.Type: GrantFiled: December 27, 2017Date of Patent: November 15, 2022Assignee: Intel CorporationInventor: Kevin Lin
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Publication number: 20220352068Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.Type: ApplicationFiled: June 15, 2022Publication date: November 3, 2022Applicant: Intel CorporationInventors: Kevin Lin, Noriyuki Sato, Tristan Tronic, Michael Christenson, Christopher Jezewski, Jiun-Ruey Chen, James M. Blackwell, Matthew Metz, Miriam Reshotko, Nafees Kabir, Jeffery Bielefeld, Manish Chandhok, Hui Jae Yoo, Elijah Karpov, Carl Naylor, Ramanan Chebiam
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Patent number: 11482622Abstract: A transistor structure includes a layer of active material on a base. The base can be insulator material in some cases. The layer has a channel region between a source region and a drain region. A gate structure is in contact with the channel region and includes a gate electrode and a gate dielectric, where the gate dielectric is between the gate electrode and the active material. An electrical contact is on one or both of the source region and the drain region. The electrical contact has a larger portion in contact with a top surface of the active material and a smaller portion extending through the layer of active material into the base. The active material may be, for example, a transition metal dichalcogenide (TMD) in some embodiments.Type: GrantFiled: December 10, 2018Date of Patent: October 25, 2022Assignee: Intel CorporationInventors: Kevin Lin, Abhishek Sharma, Carl Naylor, Urusa Alaan, Christopher Jezewski, Ashish Agrawal
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Patent number: 11469189Abstract: An integrated circuit structure comprises one or more sets of first and second conductive lines along a same direction in an interlayer dielectric (ILD), the first and second conductive lines having a width greater than 2 ?m. An air gap is in the ILD between the first and second conductive lines, the air gap extending across the ILD to sidewalls of the first and second conductive lines.Type: GrantFiled: June 29, 2018Date of Patent: October 11, 2022Assignee: Intel CorporationInventor: Kevin Lin
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Patent number: 11444024Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.Type: GrantFiled: November 2, 2020Date of Patent: September 13, 2022Assignee: Intel CorporationInventors: Kevin Lin, Noriyuki Sato, Tristan Tronic, Michael Christenson, Christopher Jezewski, Jiun-Ruey Chen, James M. Blackwell, Matthew Metz, Miriam Reshotko, Nafees Kabir, Jeffery Bielefeld, Manish Chandhok, Hui Jae Yoo, Elijah Karpov, Carl Naylor, Ramanan Chebiam
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Patent number: 11437255Abstract: A structure, comprising an island comprising a III-N material. The island extends over a substrate and has a sloped sidewall. A cap comprising a III-N material extends laterally from a top surface and overhangs the sidewall of the island. A device, such as a transistor, light emitting diode, or resonator, may be formed within, or over, the cap.Type: GrantFiled: September 27, 2017Date of Patent: September 6, 2022Assignee: Intel CorporationInventors: Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Paul Fischer, Kevin Lin
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Patent number: 11429842Abstract: A computing system is provided. The computing system includes a processor configured to execute a convolutional neural network that has been trained, the convolutional neural network including a backbone network that is a concatenated pyramid network, a plurality of first head neural networks, and a plurality of second head neural networks. At the backbone network, the processor is configured to receive an input image as input and output feature maps extracted from the input image. The processor is configured to: process the feature maps using each of the first head neural networks to output corresponding keypoint heatmaps; process the feature maps using each of the second head neural networks to output corresponding part affinity field heatmaps; link the keypoints into one or more instances of virtual skeletons using the part affinity fields; and output the instances of the virtual skeletons.Type: GrantFiled: April 26, 2019Date of Patent: August 30, 2022Assignee: Microsoft Technology Licensing, LLCInventors: Lijuan Wang, Kevin Lin, Zicheng Liu, Kun Luo