Abstract: A non-volatile semiconductor memory comprising (1) a non-volatile memory array including a plurality of blocks with at least some of the plurality of blocks comprising a plurality of memory segments and with at least some of the plurality of memory segments each assigned a physical address and (2) a volatile memory. Upon a power-up of the non-volatile semiconductor memory, a translation table is generated in the volatile memory for mapping logical addresses to physical addresses in the non-volatile memory array. The generating includes reading at least one entry comprising a logical address from an inverse map stored in the non-volatile memory array. The logical address corresponds to a physical address of one of the memory segments. In response to determining that the memory segment corresponding to the logical address is valid, the translation table is updated using the logical address.

Abstract: A non-volatile semiconductor memory is disclosed comprising a non-volatile memory array including a plurality of blocks, each block comprising a plurality of memory segments each assigned a physical address. A logical address is read from a first block, wherein the logical address corresponds to a physical address of one of the memory segments. When the memory segment corresponding to the logical address is valid, a translation table is updated using the logical address, wherein the translation table for mapping logical addresses to physical addresses. When the memory segment corresponding to the logical address is invalid, a dirty table is updated using the logical address. The dirty table is used to perform a garbage collection operation, wherein invalid memory segments are erased without being relocated.