Abstract: A multi-protocol packet translator is disclosed. The translator may have microcoded control to translate a packet from one protocol to another. The microcoded instructions may be fed through a pipeline to control reading of information from information sources (including the original packet) and selectively connecting those sources to an output memory.

Abstract: A multi-protocol packet translator is disclosed. The translator may have microcoded control to translate a packet from one protocol to another. The microcoded instructions may be fed through a pipeline to control reading of information from information sources (including the original packet) and selectively connecting those sources to an output memory.

Abstract: A system for controlling power application to an electronic component during a hotswap operation. A chassis contains a plurality of slots for interfacing with electronic components, each slot having an associated timing device. The electronic component contains a delay mechanism, such that when the electronic component interfaces with a slot in the chassis, the delay and timing mechanisms interact to create a slot timing circuit. The slot timing circuit interfaces to a ramp-up switching circuitry to produce a controlled application of power to remaining circuitry of the electronic component. The timing mechanism may be a resistor and the delay mechanism may be a capacitor, such that an RC circuit is formed which controls, in a time delayed fashion, a switching mechanism which in turn controls ramp-up of power application to the electronic component.

Abstract: A system for controlling power application to an electronic component during a hotswap operation. A chassis contains a plurality of slots for interfacing with electronic components, each slot having an associated timing device. The electronic component contains a delay mechanism, such that when the electronic component interfaces with a slot in the chassis, the delay and timing mechanisms interact to create a slot timing circuit. The slot timing circuit interfaces to a ramp-up switching circuitry to produce a controlled application of power to remaining circuitry of the electronic component. The timing mechanism may be a resistor and the delay mechanism may be a capacitor, such that an RC circuit is formed which controls, in a time delayed fashion, a switching mechanism which in turn controls ramp-up of power application to the electronic component.