Patents by Inventor Kevin M. McIlvain
Kevin M. McIlvain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11698842Abstract: A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.Type: GrantFiled: October 7, 2021Date of Patent: July 11, 2023Assignee: International Business Machines CorporationInventors: Stephen Glancy, Kyu-hyoun Kim, Warren E. Maule, Kevin M. Mcilvain
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Patent number: 11645171Abstract: A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.Type: GrantFiled: October 7, 2021Date of Patent: May 9, 2023Assignee: International Business Machines CorporationInventors: Stephen Glancy, Kyu-hyoun Kim, Warren E. Maule, Kevin M. Mcilvain
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Patent number: 11593196Abstract: A method and/or system for checking the bus/interface between a host and a memory system during memory access operations includes a memory system having one or more of the data memory devices and a spare memory device; providing a bus/interface between a host and the memory system; selecting information on a per memory device basis to associate with a spare memory device; disassociating the selected information from the one or more data memory devices and associating the selected information with the spare memory device; adding Cyclical Redundancy Check (CRC) code to the one or more data memory devices from which the selected information was disassociated; transferring the CRC code and information over the bus and interface between the host and the memory system; and checking the bus interface with the CRC code added to the one or more data memory devices.Type: GrantFiled: December 1, 2021Date of Patent: February 28, 2023Assignee: International Business Machines CorporationInventors: Kevin M. Mcilvain, Warren E. Maule, Stephen Glancy, Kyu-hyoun Kim, Edgar R. Cordero
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Patent number: 11442829Abstract: Aspects include configuring a plurality of functional self-test controllers in a test control device to run a plurality of functional test cases in parallel on a plurality of devices under test. Test traffic is arbitrated between the functional self-test controllers and a plurality of packeted protocol layer interfaces of the test control device. One or more protocol specific conversions are performed between the test traffic and a device-specific packeted protocol of each of the devices under test. Payload checking is performed between the packeted protocol layer interfaces and the devices under test to verify responses of the devices under test to the functional test cases.Type: GrantFiled: March 16, 2020Date of Patent: September 13, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ryan Patrick King, Kevin M. Mcilvain, Gary A. Van Huben
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Publication number: 20220091927Abstract: A method and/or system for checking the bus/interface between a host and a memory system during memory access operations includes a memory system having one or more of the data memory devices and a spare memory device; providing a bus/interface between a host and the memory system; selecting information on a per memory device basis to associate with a spare memory device; disassociating the selected information from the one or more data memory devices and associating the selected information with the spare memory device; adding Cyclical Redundancy Check (CRC) code to the one or more data memory devices from which the selected information was disassociated; transferring the CRC code and information over the bus and interface between the host and the memory system; and checking the bus interface with the CRC code added to the one or more data memory devices.Type: ApplicationFiled: December 1, 2021Publication date: March 24, 2022Inventors: Kevin M. Mcilvain, Warren E. Maule, Stephen Glancy, Kyu-hyoun Kim, Edgar R. Cordero
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Publication number: 20220027243Abstract: A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.Type: ApplicationFiled: October 7, 2021Publication date: January 27, 2022Inventors: Stephen Glancy, Kyu-hyoun Kim, Warren E. Maule, Kevin M. Mcilvain
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Patent number: 11200112Abstract: A method and/or system for checking the bus/interface between a host and a memory system during memory access operations includes a memory system having one or more of the data memory devices and a spare memory device; providing a bus/interface between a host and the memory system; selecting information on a per memory device basis to associate with a spare memory device; disassociating the selected information from the one or more data memory devices and associating the selected information with the spare memory device; adding Cyclical Redundancy Check (CRC) code to the one or more data memory devices from which the selected information was disassociated; transferring the CRC code and information over the bus and interface between the host and the memory system; and checking the bus interface with the CRC code added to the one or more data memory devices.Type: GrantFiled: August 24, 2020Date of Patent: December 14, 2021Assignee: International Business Machines CorporationInventors: Kevin M. Mcilvain, Warren E. Maule, Stephen Glancy, Kyu-hyoun Kim, Edgar R. Cordero
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Patent number: 11182262Abstract: A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.Type: GrantFiled: March 24, 2020Date of Patent: November 23, 2021Assignee: International Business Machines CorporationInventors: Stephen Glancy, Kyu-hyoun Kim, Warren E. Maule, Kevin M. Mcilvain
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Publication number: 20210286694Abstract: Aspects include configuring a plurality of functional self-test controllers in a test control device to run a plurality of functional test cases in parallel on a plurality of devices under test. Test traffic is arbitrated between the functional self-test controllers and a plurality of packeted protocol layer interfaces of the test control device. One or more protocol specific conversions are performed between the test traffic and a device-specific packeted protocol of each of the devices under test. Payload checking is performed between the packeted protocol layer interfaces and the devices under test to verify responses of the devices under test to the functional test cases.Type: ApplicationFiled: March 16, 2020Publication date: September 16, 2021Inventors: Ryan Patrick King, Kevin M. Mcilvain, Gary A. Van Huben
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Patent number: 11119676Abstract: Disclosed is a computer implemented method to mark data as persistent using spare bits. The method includes receiving, by a memory system, a set of data, wherein the set of data includes a subset of meta-bits, and the set of data is received as a plurality of transfers, and wherein the memory system includes a first rank and a second rank. The method also includes decoding, by a decoder, the subset of meta-bits, wherein the subset of meta-bits are configured to indicate the set of data is important. The method further includes storing, based on the decoding, the set of data in a persistent storage medium.Type: GrantFiled: November 8, 2019Date of Patent: September 14, 2021Assignee: International Business Machines CorporationInventors: Krishna Thangaraj, David D. Cadigan, Kevin M. Mcilvain
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Patent number: 11037619Abstract: A technique relates to operating a memory controller. The memory controller drives first memory devices and second memory devices of the memory controller in a dual channel mode. A first error correcting code (ECC) memory device and a second ECC memory device protect the first memory devices and the second memory devices. The memory controller drives the first memory devices and the second memory devices in a single channel mode such that the second ECC memory device is a spare memory device, and the first ECC memory device protects the first memory devices and the second memory devices. The memory controller is configured to switch between the dual channel mode and the single channel mode.Type: GrantFiled: November 5, 2019Date of Patent: June 15, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kyu-Hyoun Kim, Warren E. Maule, Kevin M. Mcilvain, Saravanan Sethuraman
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Publication number: 20210141550Abstract: Disclosed is a computer implemented method to mark data as persistent using spare bits. The method includes receiving, by a memory system, a set of data, wherein the set of data includes a subset of meta-bits, and the set of data is received as a plurality of transfers, and wherein the memory system includes a first rank and a second rank. The method also includes decoding, by a decoder, the subset of meta-bits, wherein the subset of meta-bits are configured to indicate the set of data is important. The method further includes storing, based on the decoding, the set of data in a persistent storage medium.Type: ApplicationFiled: November 8, 2019Publication date: May 13, 2021Inventors: Krishna Thangaraj, David D. Cadigan, Kevin M. McIlvain
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Publication number: 20200226040Abstract: A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.Type: ApplicationFiled: March 24, 2020Publication date: July 16, 2020Inventors: Stephen Glancy, Kyu-hyoun Kim, Warren E. Maule, Kevin M. Mcilvain
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Patent number: 10671497Abstract: A memory system for storing data is disclosed, the memory system including a plurality of memory devices configured to store data, each memory device having a plurality of bits, the memory devices configured and associated to work together as a rank to respond to a request; a memory control circuit associated with the plurality of memory devices and configured to output command and control signals to the plurality of memory devices; a detector for detecting a bit error in an operation; and a controller for remapping the bit error to a spare bit lane in response to the detector detecting the bit error.Type: GrantFiled: January 19, 2018Date of Patent: June 2, 2020Assignee: International Business Machines CorporationInventors: Stephen Glancy, Kyu-Hyoun Kim, Warren E. Maule, Kevin M. Mcilvain
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Patent number: 10642504Abstract: Embodiments of the present disclosure relate to managing volatile and non-volatile memory. A set of volatile memory sensor data may be obtained. A set of non-volatile memory sensor data may be obtained. The set of volatile memory sensor data and the set of non-volatile memory sensor data may be analyzed. A memory condition may be determined to exist based on the analysis. In response to determining that the memory condition exists, one or more memory actions may be issued.Type: GrantFiled: May 28, 2019Date of Patent: May 5, 2020Assignee: International Business Machines CorporationInventors: Briana E. Foxworth, Saravanan Sethuraman, Kevin M. Mcilvain, Lucas W. Mulkey, Adam J. McPadden
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Patent number: 10606713Abstract: A technique relates to operating a memory controller. A feedback mode is initiated such that an identified memory device of first memory devices includes an identified bit lane on a data bus to be utilized for testing. A process includes sending commands on the 1-N bit lanes of the command address bus to a buffer and duplicating commands designated for a selected one of the 1-N bit lanes. The process includes sending the duplicated commands on the identified bit lane in route to the buffer, and receiving a result of a parity check for the commands sent on the 1-N bit lanes, such that when the result is a pass the process ends. When the result is a fail, a duplicated parity check is performed using duplicated commands on the identified bit lane in place of the selected one. When the duplicated parity check passes, the selected one is bad.Type: GrantFiled: January 3, 2018Date of Patent: March 31, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kyu-hyoun Kim, Warren E. Maule, Kevin M. McIlvain, Saravanan Sethuraman
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Patent number: 10585754Abstract: An NVDIMM requests an authentication object in response to a detected command to initiate a save operation to copy first memory data located in volatile memory on the NVDIMM to non-volatile memory located on the NVDIMM. The NVDIMM determines based on the authentication object that authentication has failed. The NVDIMM implements, in response to determining that authentication has failed, a security measure to prevent recovery of the first memory data.Type: GrantFiled: August 15, 2017Date of Patent: March 10, 2020Assignee: International Business Machines CorporationInventors: Briana E. Foxworth, Saravanan Sethuraman, Lucas W. Mulkey, Adam J. McPadden, Kevin M. Mcilvain
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Publication number: 20200075079Abstract: A technique relates to operating a memory controller. The memory controller drives first memory devices and second memory devices of the memory controller in a dual channel mode. A first error correcting code (ECC) memory device and a second ECC memory device protect the first memory devices and the second memory devices. The memory controller drives the first memory devices and the second memory devices in a single channel mode such that the second ECC memory device is a spare memory device, and the first ECC memory device protects the first memory devices and the second memory devices. The memory controller is configured to switch between the dual channel mode and the single channel mode.Type: ApplicationFiled: November 5, 2019Publication date: March 5, 2020Inventors: Kyu-hyoun Kim, Warren E. Maule, Kevin M. Mcilvain, Saravanan Sethuraman
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Patent number: 10546628Abstract: A technique relates to operating a memory controller. The memory controller drives first memory devices and second memory devices of the memory controller in a dual channel mode. A first error correcting code (ECC) memory device and a second ECC memory device protect the first memory devices and the second memory devices. The memory controller drives the first memory devices and the second memory devices in a single channel mode such that the second ECC memory device is a spare memory device, and the first ECC memory device protects the first memory devices and the second memory devices. The memory controller is configured to switch between the dual channel mode and the single channel mode.Type: GrantFiled: January 3, 2018Date of Patent: January 28, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kyu-hyoun Kim, Warren E. Maule, Kevin M. McIlvain, Saravanan Sethuraman
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Publication number: 20190310896Abstract: Embodiments of the present disclosure relate to managing volatile and non-volatile memory. A set of volatile memory sensor data may be obtained. A set of non-volatile memory sensor data may be obtained. The set of volatile memory sensor data and the set of non-volatile memory sensor data may be analyzed. A memory condition may be determined to exist based on the analysis. In response to determining that the memory condition exists, one or more memory actions may be issued.Type: ApplicationFiled: May 28, 2019Publication date: October 10, 2019Inventors: Briana E. Foxworth, Saravanan Sethuraman, Kevin M. Mcilvain, Lucas W. Mulkey, Adam J. McPadden