Patents by Inventor Kevin McCullen
Kevin McCullen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070277129Abstract: A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet ‘edge coverage’ requirements.Type: ApplicationFiled: August 13, 2007Publication date: November 29, 2007Inventors: Robert Allen, Cam Endicott, Fook-Luen Heng, Jason Hibbeler, Kevin McCullen, Rani Narayan, Robert Walker, Xin Yuan
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Publication number: 20070245283Abstract: A method comprises extracting a hierarchical grid constraint set and modeling one or more critical objects of at least one cell as a variable set. The method further comprises solving a linear programming problem based on the hierarchical grid constraint set with the variable set to provide initial locations of the critical objects of the at least one cell and determining target on-grid locations of the one or more critical objects in the at least one cell using the results of the linear programming solution.Type: ApplicationFiled: April 14, 2006Publication date: October 18, 2007Inventors: Robert Allen, Michael Gray, Fuok-Luen Heng, Jason Hibbeler, Kevin McCullen, Rani Narayan, Robert Walker
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Publication number: 20070198961Abstract: A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. Also, a method, system and program product for migrating an integrated circuit design from a source technology without RDR to a target technology with RDR in which space may be reserved for late insertion of a feature and in which migration first occurs in a primary compaction direction having less tolerant ground rules.Type: ApplicationFiled: April 9, 2007Publication date: August 23, 2007Applicant: International Business Machines CorporationInventors: Robert Allen, Cam Endicott, Fook-Luen Heng, Jason Hibbeler, Kevin McCullen, Rani Narayan, Robert Walker, Xin Yuan
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Publication number: 20060101356Abstract: A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet ‘edge coverage’ requirements.Type: ApplicationFiled: October 29, 2004Publication date: May 11, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert Allen, Cam Endicott, Fook-Luen Heng, Jason Hibbeler, Kevin McCullen, Rani Narayan, Robert Walker, Xin Yuan
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Publication number: 20060101357Abstract: A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. Also, a method, system and program product for migrating an integrated circuit design from a source technology without RDR to a target technology with RDR in which space may be reserved for late insertion of a feature and in which migration first occurs in a primary compaction direction having less tolerant ground rules.Type: ApplicationFiled: December 9, 2004Publication date: May 11, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert Allen, Cam Endicott, Fook-Luen Heng, Jason Hibbeler, Kevin McCullen, Rani Narayan, Robert Walker, Xin Yuan
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Publication number: 20060085768Abstract: Methods, systems and program products are disclosed for selectively scaling an integrated circuit (IC) design: by layer, by unit, or by ground rule, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield where new technologies such as maskless fabrication are implemented.Type: ApplicationFiled: October 15, 2004Publication date: April 20, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Fook-Luen Heng, Jason Hibbeler, Kevin McCullen, Rani Narayan, Stephen Runyon, Robert Walker
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Publication number: 20060026545Abstract: A method (300) of placing a to-be-placed integrated circuit macro (404) adjacent one or more already-placed macros (400) aboard an integrated circuit chip (100). The method includes the step of performing a canonical ordering of the edges of the to-be-placed and already placed macros. Then, an edge constraint vector (500, 526) is generated for each active edge (668) of the already-placed macro(s) and each edge of the to-be-placed macro. Each of the edge constraint vectors of the to-be-placed macro is compared to each edge constraint vector of the active edge(s) using a string matching algorithm so as to determine whether any edges of the to-be-placed macro are compatible with any active edges of the already-placed macro(s). The method may be implemented in a CAD system (600).Type: ApplicationFiled: July 29, 2004Publication date: February 2, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert Allen, Steven Lovejoy, Kevin McCullen
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Publication number: 20050287443Abstract: Methods for performing phase-correct layout and routing of integrated circuits using alternating aperture phase shift masks (AltPSM), including bright field AltPSM and dark field AltPSM are disclosed. Also disclosed are systems for performing phase-correct layout and routing, including computer-based routing programs and systems.Type: ApplicationFiled: June 23, 2004Publication date: December 29, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Kevin McCullen
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Publication number: 20050240884Abstract: A method, system and program product for correcting via spacing violations by generating a redundant via to replace one of a pair of vias that violate a ground rule, are disclosed. The redundant via corrects the ground rule violation. The target via corresponding to the redundant via is then removed, which corrects the ground rule violation. The invention can be applied to any spacing ground rule including same net and different net rules, and may also be applied to a current technology or, during migration, to a new technology. The invention can be applied to different levels of a design to ensure ground rule compliance throughout the design.Type: ApplicationFiled: April 27, 2004Publication date: October 27, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Terry Frederick, Jason Hibbeler, Kevin McCullen, William Pokorny
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Publication number: 20050160390Abstract: A method, system and program product for merging cloned and original circuit shapes such that a union thereof does not include a notch. The invention determines, for a cell including an original circuit shape and at least one overlapping clone of the original circuit shape, whether each clone corner point of each overlapping clone is within a threshold distance of a corresponding original corner point of the original circuit shape; and generates, in the case that each clone corner point of each overlapping clone circuit shape is within a threshold distance, a union of each overlapping clone and the original circuit shape such that the union does not contain a notch. The union is generated using a point code that sets a new position for a union corner point to remove a notch based on the original shape's direction and the edge orientations previous to and next to the corner point.Type: ApplicationFiled: January 16, 2004Publication date: July 21, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Henry Bonges, Michael Gray, Jason Hibbeler, Kevin McCullen, Robert Walker
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Publication number: 20050125748Abstract: A method, system and program product that implements area minimization of a circuit design while respecting the explicit and implicit design constraints, in the form of ground rules and user intent. A longest path algorithm is used to generate a scaling factor. The scaling factor is used to reduce the size of the circuit design to the minimum legal size. The scaling may be followed by application of minpert analysis to correct any errors introduced by the scaling. The resulting design is shrunk (or expanded) with all elements shrinking (or growing) together by the same factor, and with the relative relationships of elements maintained. In addition, the invention is operational in the presence of a positive cycle, can be run with scaling that freezes the sizes of any structure or ground rule, and can be applied to technology migration.Type: ApplicationFiled: December 3, 2003Publication date: June 9, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Gray, Kevin McCullen, Gustavo Tellez, Robert Walker