Patents by Inventor Kevin R. Shea

Kevin R. Shea has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11355348
    Abstract: A method of forming an array comprising using two different composition masking materials in forming a pattern of spaced repeating first features of substantially same size and substantially same shape relative one another. A pattern-interrupting second feature of at least one of different size or different shape compared to that of the first features is within and interrupts the pattern of first features. The pattern of the first features with the pattern-interrupting second feature are translated into lower substrate material that is below the first features and the pattern-interrupting second feature. Material of the first features and of the pattern-interrupting second feature that is above the lower substrate material is removed at least one of during or after the translating.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: June 7, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Gurpreet Lugani, Kyle B. Campbell, Mario J. Di Cino, Aaron W. Freese, Alex Kogan, Kevin R. Shea
  • Publication number: 20200266071
    Abstract: A method of forming an array comprising using two different composition masking materials in forming a pattern of spaced repeating first features of substantially same size and substantially same shape relative one another. A pattern-interrupting second feature of at least one of different size or different shape compared to that of the first features is within and interrupts the pattern of first features. The pattern of the first features with the pattern-interrupting second feature are translated into lower substrate material that is below the first features and the pattern-interrupting second feature. Material of the first features and of the pattern-interrupting second feature that is above the lower substrate material is removed at least one of during or after the translating.
    Type: Application
    Filed: April 14, 2020
    Publication date: August 20, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Gurpreet Lugani, Kyle B. Campbell, Mario J. Di Cino, Aaron W. Freese, Alex Kogan, Kevin R. Shea
  • Patent number: 10692727
    Abstract: A method of forming an array comprising using two different composition masking materials in forming a pattern of spaced repeating first features of substantially same size and substantially same shape relative one another. A pattern-interrupting second feature of at least one of different size or different shape compared to that of the first features is within and interrupts the pattern of first features. The pattern of the first features with the pattern-interrupting second feature are translated into lower substrate material that is below the first features and the pattern-interrupting second feature. Material of the first features and of the pattern-interrupting second feature that is above the lower substrate material is removed at least one of during or after the translating.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: June 23, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Gurpreet Lugani, Kyle B. Campbell, Mario J. Di Cino, Aaron W. Freese, Alex Kogan, Kevin R. Shea
  • Publication number: 20200035498
    Abstract: A method of forming an array comprising using two different composition masking materials in forming a pattern of spaced repeating first features of substantially same size and substantially same shape relative one another. A pattern-interrupting second feature of at least one of different size or different shape compared to that of the first features is within and interrupts the pattern of first features. The pattern of the first features with the pattern-interrupting second feature are translated into lower substrate material that is below the first features and the pattern-interrupting second feature. Material of the first features and of the pattern-interrupting second feature that is above the lower substrate material is removed at least one of during or after the translating.
    Type: Application
    Filed: July 24, 2018
    Publication date: January 30, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Gurpreet Lugani, Kyle B. Campbell, Mario J. Di Cino, Aaron W. Freese, Alex Kogan, Kevin R. Shea
  • Patent number: 9741580
    Abstract: A method of forming a pattern on a substrate comprises forming spaced, upwardly-open, cylinder-like structures projecting longitudinally outward of a base. Sidewall lining is formed over inner and over outer sidewalls of the cylinder-like structures, and that forms interstitial spaces laterally outward of the cylinder-like structures. The interstitial spaces are individually surrounded by longitudinally-contacting sidewall linings that are over outer sidewalls of four of the cylinder-like structures. Other embodiments are disclosed, including structure independent of method.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: August 22, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sipani, Anton J. deVilliers, William R. Brown, Shane J. Trapp, Ranjan Khurana, Kevin R. Shea
  • Publication number: 20160027863
    Abstract: A method of forming capacitors includes providing a support material over a substrate. The support material is at least one of semiconductive or conductive. Openings are formed into the support material. The openings include at least one of semiconductive or conductive sidewalls. An insulator is deposited along the semiconductive and/or conductive opening sidewalls. A pair of capacitor electrodes having capacitor dielectric there-between is formed within the respective openings laterally inward of the deposited insulator. One of the pair of capacitor electrodes within the respective openings is laterally adjacent the deposited insulator. Other aspects are disclosed, including integrated circuitry independent of method of manufacture.
    Type: Application
    Filed: July 2, 2015
    Publication date: January 28, 2016
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Brett W. Busch, Mingtao Li, Lequn Jennifer Liu, Kevin R. Shea, Belford T. Coursey, Jonathan T. Doebler
  • Publication number: 20150206760
    Abstract: A method of forming a pattern on a substrate comprises forming spaced, upwardly-open, cylinder-like structures projecting longitudinally outward of a base. Sidewall lining is formed over inner and over outer sidewalls of the cylinder-like structures, and that forms interstitial spaces laterally outward of the cylinder-like structures. The interstitial spaces are individually surrounded by longitudinally-contacting sidewall linings that are over outer sidewalls of four of the cylinder-like structures. Other embodiments are disclosed, including structure independent of method.
    Type: Application
    Filed: March 31, 2015
    Publication date: July 23, 2015
    Inventors: Vishal Sipani, Anton J. deVilliers, William R. Brown, Shane J. Trapp, Ranjan Khurana, Kevin R. Shea
  • Patent number: 9076680
    Abstract: A method of forming capacitors includes providing a support material over a substrate. The support material is at least one of semiconductive or conductive. Openings are formed into the support material. The openings include at least one of semiconductive or conductive sidewalls. An insulator is deposited along the semiconductive and/or conductive opening sidewalls. A pair of capacitor electrodes having capacitor dielectric there-between is formed within the respective openings laterally inward of the deposited insulator. One of the pair of capacitor electrodes within the respective openings is laterally adjacent the deposited insulator. Other aspects are disclosed, including integrated circuitry independent of method of manufacture.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: July 7, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Brett W. Busch, Mingtao Li, Jennifer Lequn Liu, Kevin R. Shea, Belford T. Coursey, Jonathan T. Doebler
  • Patent number: 8999852
    Abstract: A method of forming a pattern on a substrate comprises forming spaced, upwardly-open, cylinder-like structures projecting longitudinally outward of a base. Sidewall lining is formed over inner and over outer sidewalls of the cylinder-like structures, and that forms interstitial spaces laterally outward of the cylinder-like structures. The interstitial spaces are individually surrounded by longitudinally-contacting sidewall linings that are over outer sidewalls of four of the cylinder-like structures. Other embodiments are disclosed, including structure independent of method.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: April 7, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sipani, Anton J. deVillers, William R. Brown, Shane J. Trapp, Ranjan Khurana, Kevin R. Shea
  • Publication number: 20150031212
    Abstract: Methods for etching metal nitrides and metal oxides include using ultradilute HF solutions and buffered, low-pH HF solutions containing a minimal amount of the hydrofluoric acid species H2F2. The etchant can be used to selectively remove metal nitride layers relative to doped or undoped oxides, tungsten, polysilicon, and titanium nitride. A method is provided for producing an isolated capacitor, which can be used in a dynamic random access memory cell array, on a substrate using sacrificial layers selectively removed to expose outer surfaces of the bottom electrode.
    Type: Application
    Filed: October 14, 2014
    Publication date: January 29, 2015
    Inventor: Kevin R. Shea
  • Patent number: 8889559
    Abstract: A method of forming a pattern on a substrate includes forming spaced first material-comprising pillars projecting elevationally outward of first openings formed in second material. Sidewall spacers are formed over sidewalls of the first material-comprising pillars. The sidewall spacers form interstitial spaces laterally outward of the first material-comprising pillars. The interstitial spaces are individually surrounded by longitudinally-contacting sidewall spacers that are over sidewalls of four of the first material-comprising pillars.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: November 18, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Shane J. Trapp, Ranjan Khurana, Kevin R. Shea
  • Patent number: 8883591
    Abstract: Methods for etching metal nitrides and metal oxides include using ultradilute HF solutions and buffered, low-pH HF solutions containing a minimal amount of the hydrofluoric acid species H2F2. The etchant can be used to selectively remove metal nitride layers relative to doped or undoped oxides, tungsten, polysilicon, and titanium nitride. A method is provided for producing an isolated capacitor, which can be used in a dynamic random access memory cell array, on a substrate using sacrificial layers selectively removed to expose outer surfaces of the bottom electrode.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: November 11, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Kevin R. Shea
  • Patent number: 8853050
    Abstract: Some embodiments include methods of making stud-type capacitors utilizing carbon-containing support material. Openings may be formed through the carbon-containing support material to electrical nodes, and subsequently conductive material may be grown within the openings. The carbon-containing support material may then be removed, and the conductive material utilized as stud-type storage nodes of stud-type capacitors. The stud-type capacitors may be incorporated into DRAM, and the DRAM may be utilized in electronic systems.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: October 7, 2014
    Assignee: Micron Technology
    Inventors: Mark Kiehlbauch, Kevin R. Shea
  • Patent number: 8846542
    Abstract: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: September 30, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kevin R. Shea, Thomas M. Graettinger
  • Publication number: 20140162459
    Abstract: A method of forming a pattern on a substrate includes forming spaced first material-comprising pillars projecting elevationally outward of first openings formed in second material. Sidewall spacers are formed over sidewalls of the first material-comprising pillars. The sidewall spacers form interstitial spaces laterally outward of the first material-comprising pillars. The interstitial spaces are individually surrounded by longitudinally-contacting sidewall spacers that are over sidewalls of four of the first material-comprising pillars.
    Type: Application
    Filed: December 12, 2012
    Publication date: June 12, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Shane J. Trapp, Ranjan Khurana, Kevin R. Shea
  • Publication number: 20140162430
    Abstract: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.
    Type: Application
    Filed: February 13, 2014
    Publication date: June 12, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Kevin R. Shea, Thomas M. Graettinger
  • Publication number: 20140162457
    Abstract: A method of forming a pattern on a substrate comprises forming spaced, upwardly-open, cylinder-like structures projecting longitudinally outward of a base. Sidewall lining is formed over inner and over outer sidewalls of the cylinder-like structures, and that forms interstitial spaces laterally outward of the cylinder-like structures. The interstitial spaces are individually surrounded by longitudinally-contacting sidewall linings that are over outer sidewalls of four of the cylinder-like structures. Other embodiments are disclosed, including structure independent of method.
    Type: Application
    Filed: December 12, 2012
    Publication date: June 12, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Vishal Sipani, Anton J. deVillers, William R. Brown, Shane J. Trapp, Ranjan Khurana, Kevin R. Shea
  • Patent number: 8691704
    Abstract: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: April 8, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kevin R. Shea, Thomas M. Graettinger
  • Patent number: 8692305
    Abstract: Semiconductor device structures include an at least partially formed container capacitor having a generally cylindrical first conductive member with at least one inner sidewall surface, a lattice material at least partially laterally surrounding an upper end portion of the first conductive member, an anchor material, and at least one aperture extending through the lattice material between the at least partially formed container capacitor and an adjacent at least partially formed container capacitor. Other structures include an at least partially formed container capacitor, a lattice material, and an anchor material disposed over a surface of the lattice material and at least a portion of an end surface of the first conductive member and forming a chemical barrier over at least a portion of an interface between the lattice material and the upper end portion of the first conductive member.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: April 8, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Brett Busch, Kevin R. Shea, Thomas A. Figura
  • Patent number: 8623725
    Abstract: A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield is etched through within the opening. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: January 7, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Mark Kiehlbauch, Kevin R. Shea