Abstract: Novel tools and techniques are provided for implementing network experience shifting, and, in particular embodiments, using either a roaming or portable hypervisor associated with a user or a local hypervisor unassociated with the user. In some embodiments, a network node in a first network might receive, via a first network access device in a second network, a request from a user device to establish roaming network access, and might authenticate a user associated with the user device, the user being unassociated with the first network access device. Based on a determination that the user is authorized to access data, content, profiles, and/or software applications that are accessible via a second network access device, the network node might establish a secure private connection through a hypervisor or container communicatively coupled to the first network access device to provide the user with access to her data, content, profiles, and/or software applications.

Abstract: A system and method for efficiently monitoring traces of multiple components in an embedded system. A system-on-a-chip (SOC) includes a trace unit for collecting and storing trace history, bus event statistics, or both. The SOC may transfer cache coherent messages across multiple buses between a shared memory and a cache coherent controller. The trace unit includes multiple bus event filters. Programmable configuration registers are used to assign the bus event filters to selected buses for monitoring associated bus traffic and determining whether qualified bus events occur. If so, the bus event filters increment an associated count for each of the qualified bus events. The values used for determining qualified bus events may be set by programmable configuration registers.

Abstract: A system and method for efficiently storing traces of multiple components in an embedded system. A system-on-a-chip (SOC) includes a trace unit for collecting and storing trace history, bus event statistics, or both. The SOC may transfer cache coherent messages across multiple buses between a shared memory and a cache coherent controller. The trace unit includes a trace buffer with multiple physical partitions assigned to subsets of the multiple buses. The number of partitions is less than the number of multiple buses. One or more trace instructions may cause a trace history, trace bus event statistics, local time stamps and a global time-base value to be stored in a physical partition within the trace buffer.

Abstract: A debug port configured to generate and provide a return clock is disclosed. In one embodiment, an integrated circuit (IC) includes one or more functional units and a debug port (DP). The DP is configured to enable access by an external debugger to the functional unit(s) of the IC for debugging purposes. The DP includes circuitry that may generate a first clock signal that is provided to the functional unit(s) during debug operations. Receiving test result data at the DP may require a return clock signal that is not provided by the functional unit(s). Accordingly, the IC may include a clock modifier coupled to receive the first clock signal. The clock modifier may generate a second clock signal based on the first, the second clock signal being provided to the DP as a return clock signal.

Abstract: A method and apparatus of stopping a functional block of an integrated circuit (IC) for debugging purposes is disclosed. In one embodiment, an IC includes a number of functional units accessible by an external debugger via a debug port (DP). During a debug operation, a power controller in the IC may power down a functional unit. When the functional unit is powered off, a first register may be programmed. Responsive to the programming of the first register, a first signal may be asserted and provided to the functional unit. When power is restored to the functional unit, operation of the functional unit may be halted prior to execution of instructions or other operations, responsive to the signal.

Abstract: A system and method for efficiently monitoring traces of multiple components in an embedded system. A system-on-a-chip (SOC) includes a trace unit for collecting and storing trace history, bus event statistics, or both. The SOC may transfer cache coherent messages across multiple buses between a shared memory and a cache coherent controller. The trace unit includes multiple bus event filters. Programmable configuration registers are used to assign the bus event filters to selected buses for monitoring associated bus traffic and determining whether qualified bus events occur. If so, the bus event filters increment an associated count for each of the qualified bus events. The values used for determining qualified bus events may be set by programmable configuration registers.

Abstract: A system and method for efficiently storing traces of multiple components in an embedded system. A system-on-a-chip (SOC) includes a trace unit for collecting and storing trace history, bus event statistics, or both. The SOC may transfer cache coherent messages across multiple buses between a shared memory and a cache coherent controller. The trace unit includes a trace buffer with multiple physical partitions assigned to subsets of the multiple buses. The number of partitions is less than the number of multiple buses. One or more trace instructions may cause a trace history, trace bus event statistics, local time stamps and a global time-base value to be stored in a physical partition within the trace buffer.

Abstract: In one embodiment, an integrated circuit comprises a first processor configured to output program counter (PC) trace records, wherein PC trace records provide data indicating the PCs of instructions retired by the first processor. The integrated circuit further comprises a second source of trace records, and a trace unit coupled to receive the PC trace records from the first processor and the trace records from the second source. The trace unit comprises a trace memory into which the trace unit is configured to store the PC trace records and trace records from the second source. The trace unit is configured to interleave the PC trace records and the trace records from the second source in the trace memory according to the order of receipt of the records.

Abstract: A method and apparatus of stopping a functional block of an integrated circuit (IC) for debugging purposes is disclosed. In one embodiment, an IC includes a number of functional units accessible by an external debugger via a debug port (DP). During a debug operation, a power controller in the IC may power down a functional unit. When the functional unit is powered off, a first register may be programmed. Responsive to the programming of the first register, a first signal may be asserted and provided to the functional unit. When power is restored to the functional unit, operation of the functional unit may be halted prior to execution of instructions or other operations, responsive to the signal.

Abstract: In one embodiment, an integrated circuit comprises a first processor configured to output program counter (PC) trace records, wherein PC trace records provide data indicating the PCs of instructions retired by the first processor. The integrated circuit further comprises a second source of trace records, and a trace unit coupled to receive the PC trace records from the first processor and the trace records from the second source. The trace unit comprises a trace memory into which the trace unit is configured to store the PC trace records and trace records from the second source. The trace unit is configured to interleave the PC trace records and the trace records from the second source in the trace memory according to the order of receipt of the records.

Abstract: A debug port configured to generate and provide a return clock is disclosed. In one embodiment, an integrated circuit (IC) includes one or more functional units and a debug port (DP). The DP is configured to enable access by an external debugger to the functional unit(s) of the IC for debugging purposes. The DP includes circuitry that may generate a first clock signal that is provided to the functional unit(s) during debug operations. Receiving test result data at the DP may require a return clock signal that is not provided by the functional unit(s). Accordingly, the IC may include a clock modifier coupled to receive the first clock signal. The clock modifier may generate a second clock signal based on the first, the second clock signal being provided to the DP as a return clock signal.

Abstract: A method and apparatus of stopping a functional block of an integrated circuit (IC) for debugging purposes is disclosed. In one embodiment, an IC includes a number of functional units accessible by an external debugger via a debug port (DP). During a debug operation, a power controller in the IC may power down a functional unit. When the functional unit is powered off, a first register may be programmed. Responsive to the programming of the first register, a first signal may be asserted and provided to the functional unit. When power is restored to the functional unit, operation of the functional unit may be halted prior to execution of instructions or other operations, responsive to the signal.

Abstract: In one embodiment, an integrated circuit comprises a first processor configured to output program counter (PC) trace records, wherein PC trace records provide data indicating the PCs of instructions retired by the first processor. The integrated circuit further comprises a second source of trace records, and a trace unit coupled to receive the PC trace records from the first processor and the trace records from the second source. The trace unit comprises a trace memory into which the trace unit is configured to store the PC trace records and trace records from the second source. The trace unit is configured to interleave the PC trace records and the trace records from the second source in the trace memory according to the order of receipt of the records.

Abstract: In one embodiment, an integrated circuit comprises a first processor configured to output program counter (PC) trace records, wherein PC trace records provide data indicating the PCs of instructions retired by the first processor. The integrated circuit further comprises a second source of trace records, and a trace unit coupled to receive the PC trace records from the first processor and the trace records from the second source. The trace unit comprises a trace memory into which the trace unit is configured to store the PC trace records and trace records from the second source. The trace unit is configured to interleave the PC trace records and the trace records from the second source in the trace memory according to the order of receipt of the records.

Abstract: In one embodiment, an integrated circuit comprises a first processor configured to output program counter (PC) trace records, wherein PC trace records provide data indicating the PCs of instructions retired by the first processor. The integrated circuit further comprises a second source of trace records, and a trace unit coupled to receive the PC trace records from the first processor and the trace records from the second source. The trace unit comprises a trace memory into which the trace unit is configured to store the PC trace records and trace records from the second source. The trace unit is configured to interleave the PC trace records and the trace records from the second source in the trace memory according to the order of receipt of the records.

Abstract: In one embodiment, an integrated circuit comprises a first processor configured to output program counter (PC) trace records, wherein PC trace records provide data indicating the PCs of instructions retired by the first processor. The integrated circuit further comprises a second source of trace records, and a trace unit coupled to receive the PC trace records from the first processor and the trace records from the second source. The trace unit comprises a trace memory into which the trace unit is configured to store the PC trace records and trace records from the second source. The trace unit is configured to interleave the PC trace records and the trace records from the second source in the trace memory according to the order of receipt of the records.

Abstract: In one embodiment, an integrated circuit comprises a first processor configured to output program counter (PC) trace records, wherein PC trace records provide data indicating the PCs of instructions retired by the first processor. The integrated circuit further comprises a second source of trace records, and a trace unit coupled to receive the PC trace records from the first processor and the trace records from the second source. The trace unit comprises a trace memory into which the trace unit is configured to store the PC trace records and trace records from the second source. The trace unit is configured to interleave the PC trace records and the trace records from the second source in the trace memory according to the order of receipt of the records.