Patents by Inventor Kevin R. Winstel
Kevin R. Winstel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10615139Abstract: A wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.Type: GrantFiled: April 5, 2018Date of Patent: April 7, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wei Lin, Leathen Shi, Spyridon Skordas, Kevin R. Winstel
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Patent number: 10211178Abstract: A wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.Type: GrantFiled: April 19, 2017Date of Patent: February 19, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wei Lin, Leathen Shi, Spyridon Skordas, Kevin R. Winstel
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Patent number: 10134577Abstract: Edge trim processes in 3D integrated circuits and resultant structures are provided. The method includes trimming an edge of a wafer at an angle to form a sloped sidewall. The method further includes attaching the wafer to a carrier wafer with a smaller diameter lower portion of the wafer bonded to the carrier wafer. The method further includes thinning the wafer while it is attached to the wafer.Type: GrantFiled: May 21, 2015Date of Patent: November 20, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Richard F. Indyk, Deepika Priyadarshini, Spyridon Skordas, Edmund J. Sprogis, Anthony K. Stamper, Kevin R. Winstel
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Publication number: 20180226374Abstract: A wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.Type: ApplicationFiled: April 5, 2018Publication date: August 9, 2018Inventors: Wei Lin, Leathen Shi, Spyridon Skordas, Kevin R. Winstel
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Patent number: 10020279Abstract: A wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.Type: GrantFiled: July 13, 2016Date of Patent: July 10, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wei Lin, Leathen Shi, Spyridon Skordas, Kevin R. Winstel
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Publication number: 20170221850Abstract: A wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.Type: ApplicationFiled: April 19, 2017Publication date: August 3, 2017Inventors: Wei Lin, Leathen Shi, Spyridon Skordas, Kevin R. Winstel
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Patent number: 9620481Abstract: A metallic dopant element having a greater oxygen-affinity than copper is introduced into, and/or over, surface portions of copper-based metal pads and/or surfaces of a dielectric material layer embedding the copper-based metal pads in each of two substrates to be subsequently bonded. A dopant-metal silicate layer may be formed at the interface between the two substrates to contact portions of metal pads not in contact with a surface of another metal pad, thereby functioning as an oxygen barrier layer, and optionally as an adhesion material layer. A dopant metal rich portion may be formed in peripheral portions of the metal pads in contact with the dopant-metal silicate layer. A dopant-metal oxide portion may be formed in peripheral portions of the metal pads that are not in contact with a dopant-metal silicate layer.Type: GrantFiled: May 19, 2015Date of Patent: April 11, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Daniel C. Edelstein, Douglas C. La Tulipe, Jr., Wei Lin, Deepika Priyadarshini, Spyridon Skordas, Tuan A. Vo, Kevin R. Winstel
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Patent number: 9553054Abstract: Strain detection structures used with bonded wafers and chips and methods of manufacture are disclosed. The method includes forming lower metal wiring structures associated with a lower wafer structure. The method further includes bonding the lower wafer structure to an upper wafer structure and thinning the upper wafer, and forming upper metal wiring structures. The method further includes electrically linking the lower metal wiring structures to the upper metal wiring structures by formation of through silicon via structures to form an electrically connected chain extending between multiple wafer structures. The method further includes forming contacts to an outside environment which electrically contact two of the lower metal wiring structures.Type: GrantFiled: October 23, 2014Date of Patent: January 24, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Mukta G. Farooq, John A. Fitzsimmons, Erdem Kaltalioglu, Wei Lin, Spyridon Skordas, Kevin R. Winstel
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Patent number: 9543229Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip.Type: GrantFiled: December 27, 2013Date of Patent: January 10, 2017Assignee: International Business Machines CorporationInventors: Pooja R. Batra, John W. Golz, Subramanian S. Iyer, Douglas C. La Tulipe, Jr., Spyridon Skordas, Kevin R. Winstel
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Patent number: 9536809Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip.Type: GrantFiled: August 30, 2015Date of Patent: January 3, 2017Assignee: International Business Machines CorporationInventors: Pooja R. Batra, John W. Golz, Subramanian S. Iyer, Douglas C. La Tulipe, Jr., Spyridon Skordas, Kevin R. Winstel
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Patent number: 9536853Abstract: According to at least one embodiment of the present invention, a wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.Type: GrantFiled: November 18, 2014Date of Patent: January 3, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wei Lin, Leathen Shi, Spyridon Skordas, Kevin R. Winstel
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Publication number: 20160343564Abstract: Edge trim processes in 3D integrated circuits and resultant structures are provided. The method includes trimming an edge of a wafer at an angle to form a sloped sidewall. The method further includes attaching the wafer to a carrier wafer with a smaller diameter lower portion of the wafer bonded to the carrier wafer. The method further includes thinning the wafer while it is attached to the wafer.Type: ApplicationFiled: May 21, 2015Publication date: November 24, 2016Inventors: Richard F. INDYK, Deepika PRIYADARSHINI, Spyridon SKORDAS, Edmund J. SPROGIS, Anthony K. STAMPER, Kevin R. WINSTEL
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Publication number: 20160322324Abstract: A wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.Type: ApplicationFiled: July 13, 2016Publication date: November 3, 2016Inventors: Wei Lin, Leathen Shi, Spyridon Skordas, Kevin R. Winstel
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Patent number: 9401303Abstract: The present invention relates generally to semiconductor structures and methods of manufacture and, more particularly, to the temporary bonding of a semiconductor wafer to handler wafer during processing. The semiconductor wafer may be temporarily bonded to the handler wafer by forming a sacrificial layer on a surface of a handler wafer, forming a first dielectric layer on a surface of the sacrificial layer, forming a second dielectric layer on a surface of a semiconductor wafer, and directly bonding the first dielectric layer and the second dielectric layer to form a bonding layer. After the semiconductor wafer is processed, it may be removed from the handler wafer along with the bonding layer by degrading the sacrificial layer with infrared radiation transmitted through the handler wafer.Type: GrantFiled: August 1, 2014Date of Patent: July 26, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Kangguo Cheng, Jonathan E. Faltermeier, Mukta G. Farooq, Wei Lin, Spyridon Skordas, Kevin R. Winstel
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Patent number: 9378966Abstract: A method of preparing an etch solution and thinning semiconductor wafers using the etch solution is proposed. The method includes steps of creating a mixture of hydrofluoric acid, nitric acid, and acetic acid in a solution container in an approximate 1:3:5 ratio; causing the mixture to react with portions of one or more silicon wafers, the portions of the one or more silicon wafers are doped with boron in a level no less than 1×1019 atoms/cm3; collecting the mixture after reacting with the boron doped portions of the one or more silicon wafers; and adding collected mixture back into the solution container to create the etch solution.Type: GrantFiled: June 10, 2014Date of Patent: June 28, 2016Assignee: International Business Machines CorporationInventors: Brown C. Peethala, Spyridon Skordas, Da Song, Allan Upham, Kevin R. Winstel
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Publication number: 20160141263Abstract: According to at least one embodiment of the present invention, a wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.Type: ApplicationFiled: November 18, 2014Publication date: May 19, 2016Inventors: Wei Lin, Leathen Shi, Spyridon Skordas, Kevin R. Winstel
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Publication number: 20160118348Abstract: Strain detection structures used with bonded wafers and chips and methods of manufacture are disclosed. The method includes forming lower metal wiring structures associated with a lower wafer structure. The method further includes bonding the lower wafer structure to an upper wafer structure and thinning the upper wafer, and forming upper metal wiring structures. The method further includes electrically linking the lower metal wiring structures to the upper metal wiring structures by formation of through silicon via structures to form an electrically connected chain extending between multiple wafer structures. The method further includes forming contacts to an outside environment which electrically contact two of the lower metal wiring structures.Type: ApplicationFiled: October 23, 2014Publication date: April 28, 2016Inventors: Mukta G. FAROOQ, John A. FITZSIMMONS, Erdem KALTALIOGLU, Wei LIN, Spyridon SKORDAS, Kevin R. WINSTEL
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Publication number: 20160035616Abstract: The present invention relates generally to semiconductor structures and methods of manufacture and, more particularly, to the temporary bonding of a semiconductor wafer to handler wafer during processing. The semiconductor wafer may be temporarily bonded to the handler wafer by forming a sacrificial layer on a surface of a handler wafer, forming a first dielectric layer on a surface of the sacrificial layer, forming a second dielectric layer on a surface of a semiconductor wafer, and directly bonding the first dielectric layer and the second dielectric layer to form a bonding layer. After the semiconductor wafer is processed, it may be removed from the handler wafer along with the bonding layer by degrading the sacrificial layer with infrared radiation transmitted through the handler wafer.Type: ApplicationFiled: August 1, 2014Publication date: February 4, 2016Inventors: Kangguo Cheng, Johnathan E. Faltermeier, Mukta G. Farooq, Wei Lin, Spyridon Skordas, Kevin R. Winstel
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Publication number: 20150371927Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a 3D integration scheme for multiple semiconductor wafers using an arrangement of intra-wafer through silicon vias (TSVs) to electrically connect the front side of a first integrated circuit (IC) chip to large back side wiring on the back side of the first IC chip and inter-wafer TSVs to electrically connect the first IC chip to a second IC chip.Type: ApplicationFiled: August 30, 2015Publication date: December 24, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pooja R. Batra, John W. Golz, Subramanian S. Iyer, Douglas C. La Tulipe, JR., Spyridon Skordas, Kevin R. Winstel
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Patent number: 9214435Abstract: Circuits incorporating three-dimensional integration and methods of their fabrication are disclosed. One circuit includes a bottom layer and a plurality of upper layers. The bottom layer includes a bottom landing pad connected to functional components in the bottom layer. In addition, the upper layers are stacked above the bottom layer. Each of the upper layers includes a respective upper landing pad that is connected to respective functional components in the respective upper layer. The landing pads are coupled by a single conductive via and are aligned in a stack of the bottom layer and the upper layers such that each of the landing pads is offset from any of the landing pads in an adjacent layer in the stack by at least one pre-determined amount.Type: GrantFiled: May 21, 2012Date of Patent: December 15, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Mukta G. Farooq, Troy L. Graves-Abe, Spyridon Skordas, Kevin R. Winstel