Patents by Inventor Kevin Safford
Kevin Safford has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230095914Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, and a die module coupled to the package substrate. In an embodiment, the die module comprises a die and a chiplet coupled to the die. In an embodiment, the chiplet is coupled to the die with a hybrid bonding interconnect architecture.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Inventors: Gerald PASDAST, Sathya Narasimman TIAGARAJ, Adel A. ELSHERBINI, Tanay KARNIK, Robert MUNOZ, Kevin SAFFORD
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Patent number: 10846439Abstract: A system to evaluate functional safety in an integrated circuit. The system includes a first circuit to execute an operation to cause to system to perform a function, where the function associated with a specified safety integrity level. The system also includes second circuit to capture trace data at an interface to the first circuit or at internal signals without inhibiting performance of the function, where the trace data comprising information that is used to determine whether the system can perform the function with an indicated level of functional safety and transmit the trace data to a safety evaluation circuit.Type: GrantFiled: June 28, 2019Date of Patent: November 24, 2020Assignee: Intel CorporationInventors: Riccardo Locatelli, Peter Lachner, Riccardo Mariani, Michael Paulitsch, Kevin Safford
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Publication number: 20200280526Abstract: Embodiments include apparatuses, methods, and systems of routing network containing a set of sources, a primary destination, a set of secondary destinations, and one or more routing elements. A routing element includes an input port, a set of output ports including a primary output port and a set of secondary output ports, and a control unit. The control unit is arranged to select a secondary output port to deliver a received message when the intended destination of the message is a secondary destination and the secondary output port is in a functional state. Otherwise, the control unit is arranged to select the primary output port to deliver the received message to the primary destination when the intended destination is the secondary destination and the secondary output port that reaches the secondary destination is in a nonfunctional state. Other embodiments may also be described and claimed.Type: ApplicationFiled: May 18, 2020Publication date: September 3, 2020Inventors: Kevin Safford, Victor Ruybalid
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Patent number: 10725848Abstract: Embodiment of this disclosure provides a mechanism to support hang detection and data recovery in microprocessor systems. In one embodiment, a processing device comprising a processing core and a crashlog unit operatively coupled to the core is provided. An indication of an unresponsive state in an execution of a pending instruction by the core is received. Responsive to receiving the indication, a crash log comprising data from registers of at least one of: a core region, a non-core region and a controller hub associated with the processing device is produced. Thereupon, the crash log is stored in a shared memory of a power management controller (PMC) associated with the controller hub.Type: GrantFiled: February 7, 2018Date of Patent: July 28, 2020Assignee: Intel CorporationInventors: Tsvika Kurts, Ki W. Yoon, Michael J. St. Clair, Larisa Novakovsky, Hisham Shafi, William H. Penner, Yoni Aizik, Kevin Safford, Hermann Gartler
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Publication number: 20190370503Abstract: A system to evaluate functional safety in an integrated circuit. The system includes a first circuit to execute an operation to cause to system to perform a function, where the function associated with a specified safety integrity level. The system also includes second circuit to capture trace data at an interface to the first circuit or at internal signals without inhibiting performance of the function, where the trace data comprising information that is used to determine whether the system can perform the function with an indicated level of functional safety and transmit the trace data to a safety evaluation circuit.Type: ApplicationFiled: June 28, 2019Publication date: December 5, 2019Inventors: Riccardo Locatelli, Peter Lachner, Riccardo Mariani, Michael Paulitsch, Kevin Safford
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Publication number: 20190243701Abstract: Embodiment of this disclosure provides a mechanism to support hang detection and data recovery in microprocessor systems. In one embodiment, a processing device comprising a processing core and a crashlog unit operatively coupled to the core is provided. An indication of an unresponsive state in an execution of a pending instruction by the core is received. Responsive to receiving the indication, a crash log comprising data from registers of at least one of: a core region, a non-core region and a controller hub associated with the processing device is produced. Thereupon, the crash log is stored in a shared memory of a power management controller (PMC) associated with the controller hub.Type: ApplicationFiled: February 7, 2018Publication date: August 8, 2019Inventors: Tsvika Kurts, Ki W. Yoon, Michael J. St. Clair, Larisa Novakovsky, Hisham Shafi, William H. Penner, Yoni Aizik, Kevin Safford, Hermann Gartler
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Patent number: 9641556Abstract: A social analytic system collects signals from different social network accounts. Social metrics are derived for the accounts and the accounts classified as different types of constituents for a company or primary account based on the social metrics. The constituents may include any combination of advocates, detractors, influencers, spammers, employees, partners, and/or market. Some of the social metrics used for classifying the different types of constituents may include a volume of the signals, types of message interactions, number of unique messages, sentiment, number of subscribers, alignment of constituent and company messages, and/or average signal length.Type: GrantFiled: November 20, 2012Date of Patent: May 2, 2017Assignee: Sprinklr, Inc.Inventors: Timothy Joseph Potter, Kevin Safford, Jason Westigard, II, John Joseph De Olivera, Erik Lee Huddleston, Bryan Horne, David Chi-Fine Yu, Brandon Kearby, Stephen Michael Vaughan, II
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Patent number: 9288123Abstract: A social analytic system may collect social signals from different social network accounts. The social signals may be associated with different ecosystems. Time series data may be generated from the social signals and the time series data may be filtered to remove at least some generic or unrelated trends. Different data sets from the time series data may be associated with different ecosystem metrics. The social analytic system may compare different filtered time series data sets to identify different ecosystem events. For example, the comparisons may be used to identify highly correlated ecosystem metrics and ecosystem anomalies, and predict ecosystem events.Type: GrantFiled: December 7, 2012Date of Patent: March 15, 2016Assignee: SPRINKLR, INC.Inventors: Kevin Safford, John Joseph De Oliveira, Erik Lee Hudleston, Brian Huddleston
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Patent number: 8886979Abstract: Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.Type: GrantFiled: June 10, 2013Date of Patent: November 11, 2014Assignee: Intel CorporationInventors: Kevin Safford, Rohit Bhatia, Chris Bostak, Richard Blumberg, Blaine Stackhouse, Steve Undy
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Publication number: 20130275787Abstract: Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.Type: ApplicationFiled: June 10, 2013Publication date: October 17, 2013Inventors: Kevin Safford, Rohit Bhatia, Chris Bostak, Richard Blumberg, Blaine Stackhouse, Steve Undy
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Patent number: 8479029Abstract: Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.Type: GrantFiled: June 24, 2011Date of Patent: July 2, 2013Assignee: Intel CorporationInventors: Kevin Safford, Rohit Bhatia, Chris Bostak, Richard Blumberg, Blaine Stackhouse, Steve Undy
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Publication number: 20110252255Abstract: Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.Type: ApplicationFiled: June 24, 2011Publication date: October 13, 2011Inventors: Kevin Safford, Rohit Bhatia, Chris Bostak, Richard Blumberg, Blaine Stackhouse, Steve Undy
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Patent number: 7992017Abstract: Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.Type: GrantFiled: September 11, 2007Date of Patent: August 2, 2011Assignee: Intel CorporationInventors: Kevin Safford, Rohit Bhatia, Chris Bostak, Richard Blumberg, Blaine Stackhouse, Steve Undy
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Publication number: 20090070607Abstract: Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a processor to determine the types of instructions that it has, calculating power consumption by in an execution period based on the types of instructions, and limiting the execution to a subset of instructions of the number to control the quantity of power for the execution period. Some embodiments may also create artificial activity to provide a minimum power floor for the processor. Apparatus embodiments comprise instruction type determination logic to determine types of instructions in an incoming instruction stream, a power calculator to calculate power consumption associated with processing a number of instructions in an execution period, and instruction throttling logic to control the power consumption by limiting the number of instructions to be processed in the execution period.Type: ApplicationFiled: September 11, 2007Publication date: March 12, 2009Inventors: Kevin Safford, Rohit Bhatia, Chris Bostak, Richard Blumberg, Blaine Stackhouse, Steve Undy
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Patent number: 7409524Abstract: The present invention relates to an improved microprocessor having a memory system with several caches that can be operated to provide virtual memory. Among the caches included in the microprocessor are conventional caches that store data and instructions to be utilized by the processes being performed by the microprocessor, and that are typically arranged in a cache hierarchy, as well as one or more translation lookaside buffer (TLB) caches that store a limited number of virtual page translations. The improved microprocessor also has an additional cache that serves to store a virtual hash page table (VHPT) that is accessed when TLB misses occur. The introduction of this VHPT cache eliminates or at least reduces the need for the microprocessor to look for information within the caches of the cache hierarchy or in other memory (e.g., main memory) outside of the microprocessor when TLB misses occur, and consequently enhances microprocessor speed.Type: GrantFiled: August 17, 2005Date of Patent: August 5, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Kevin Safford, Rohit Bhatia, Karl Brummel
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Publication number: 20070061812Abstract: An apparatus for communicating between lock step is incorporated on two or more processors operating in a lock step mode. Each of the processors includes processor logic to execute a code sequence, and an identical code sequence is executed by the processor logic. The apparatus further includes a processor-specific resource referenced by the code sequence. A multiplexer is coupled to the processor-specific resource, and is controlled to read data based on the identification. Coupled to the processors is a lock step logic block operable to read and compare the output of each of the processors. The lock step logic determines if operation of the processors is in a lock step mode or in an independent processor mode. Such determination may be made by the lock step logic turning off, for example.Type: ApplicationFiled: November 14, 2006Publication date: March 15, 2007Inventors: Kevin Safford, Jeremy Petsinger
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Publication number: 20070043929Abstract: The present invention relates to an improved microprocessor having a memory system with several caches that can be operated to provide virtual memory. Among the caches included in the microprocessor are conventional caches that store data and instructions to be utilized by the processes being performed by the microprocessor, and that are typically arranged in a cache hierarchy, as well as one or more translation lookaside buffer (TLB) caches that store a limited number of virtual page translations. The improved microprocessor also has an additional cache that serves to store a virtual hash page table (VHPT) that is accessed when TLB misses occur. The introduction of this VHPT cache eliminates or at least reduces the need for the microprocessor to look for information within the caches of the cache hierarchy or in other memory (e.g., main memory) outside of the microprocessor when TLB misses occur, and consequently enhances microprocessor speed.Type: ApplicationFiled: August 17, 2005Publication date: February 22, 2007Inventors: Kevin Safford, Rohit Bhatia, Karl Brummel
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Publication number: 20060248384Abstract: An apparatus, operating on an advanced multi-core processor architecture, and a corresponding method, are used to enhance recovery from loss of lock step in a multi-processor computer system. The apparatus for recovery from loss of lock step includes multiple processor units operating in the computer system, each of the processor units having at least two processor units operating in lock step, and at least one idle processor unit operating in lock step; and a controller coupled to the two processor units operating in lock step and the idle processor unit. The controller includes mechanisms for copying an architected state of each of the two lock step processor units to the idle processor unit.Type: ApplicationFiled: June 16, 2006Publication date: November 2, 2006Inventor: Kevin Safford
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Publication number: 20060085677Abstract: An apparatus, and a corresponding method, are used for seeding differences in lock stepped processors, the apparatus implemented on two or more processors operating in a lock step mode. Each of the two or more processors comprise a processor-specific resource operable to seed the differences, a processor logic to execute a code sequence, in which an identical code sequence is executed by the processor logic of each of the two or more processors, and an output to provide a result of execution of the code sequence. The processor outputs, based on execution of the code sequence is provided to a lock step logic operable to read and compare the output of each of the two or more processors.Type: ApplicationFiled: December 1, 2005Publication date: April 20, 2006Inventors: Kevin Safford, Jeremy Petsinger
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Publication number: 20060036424Abstract: Computer system models and methods for modeling computers that share resources are disclosed herein. One embodiment of the method for modeling a computer system comprises modeling a first shared resource and associating a first model of the first shared resource with a first processor model. A second model of the first shared resource is associated with a second processor model, wherein the first model of the first shared resource is substantially identical to the second model of the first shared resource. Data associated with the first model of the first shared resource is maintained to be equal to the data associated with the second model of the first shared resource.Type: ApplicationFiled: August 13, 2004Publication date: February 16, 2006Inventors: Jeremy Petsinger, Danny Kwong, Kevin Safford