Abstract: A converter includes a first circuit. The first circuit includes a first input that receives a power supply signal, a second input that receives a first signal, and a first output that outputs a second signal having an amplitude that is based on a frequency of the first signal. The first signal is based on an error value and a third signal, and the third signal is independent of feedback of the first circuit. The converter also includes a second circuit having a second output coupled to the second input and that outputs the third signal. The second circuit nonlinearly adapts the third signal based on the power supply signal and a reference signal.

Abstract: A converter includes a first circuit. The first circuit includes a first input that receives a power supply signal, a second input that receives a first signal, and a first output that outputs a second signal having an amplitude that is based on a frequency of the first signal. The first signal is based on an error value and a third signal, and the third signal is independent of feedback of the first circuit. The converter also includes a second circuit having a second output coupled to the second input and that outputs the third signal. The second circuit nonlinearly adapts the third signal based on the power supply signal and a reference signal.

Abstract: A Switch Node Assisted Linear architecture, including a linear amplifier in parallel with a switched converter, is configurable in two tracking modes: (a) a SMAL regulator in which the amplifier sets load voltage with an envelope tracking bandwidth, and the switched converter is configured for current assist, and (b) a Switched Mode Power Supply configuration in which the amplifier is switch-decoupled, and the switcher circuit is switched configured with an output capacitor, operable as an SMPS providing load voltage with an adaptive tracking bandwidth that is less than the envelope tracking bandwidth.

Abstract: The disclosed switched mode assisted linear (SMAL) amplifier/regulator architecture may be configured as a SMAL regulator to supply power to a dynamic load, such as an RF power amplifier. Embodiments of a SMAL regulator include configurations in which a linear amplifier and a switched mode converter (switcher) parallel coupled at a supply node, and configured such that the amplifier sets load voltage, while the amplifier and the switched mode converter are cooperatively controlled to supply load current. In one embodiment, the linear amplifier is AC coupled to the supply node, and the switched converter is configured with a capacitive charge control loop that controls the switched converter to effectively control the amplifier to provide capacitive charge control.

Abstract: A switched mode assisted linear regulator includes a linear amplifier (LA) and a buck converter configured as a current source. In example embodiments, the buck converter circuit includes a power switch M1 with an M1 body diode (tub), and includes buck turn-off circuitry configured to avoid negative inductor current by controlled switching of the tub to the higher of VIN and a second voltage. For DC-coupled configurations, boost functionality is provided by an LA boost supply, and the tub is switched to the boost supply. For AC-coupled configurations, boost functionality can be provided without boosting the LA supply rail by constraining signal peak-to-peak amplitude to be less than the LA supply voltage (maintaining a DC-average voltage on the AC-coupling capacitor), and the tub is switched to the higher of VIN and VOUT. The buck turn-off circuitry can include zero crossing detection to control M1 tub switches.

Abstract: A Switch Node Assisted Linear architecture, including a linear amplifier in parallel with a switched converter, is configurable in two tracking modes: (a) a SMAL regulator in which the amplifier sets toad voltage with an envelope tracking bandwidth, and the switched converter is configured for current assist, and (b) a Switched Mode Power Supply configuration in which the amplifier is switch-decoupled, and the switcher circuit is switched configured with an output capacitor, operable as an SMPS providing load voltage with an adaptive tracking bandwidth that is less than the envelope tracking bandwidth.

Abstract: A switched mode assisted linear regulator includes a linear amplifier (LA) and a buck converter configured as a current source. In example embodiments, the buck converter circuit includes a power switch M1 with an M1 body diode (tub), and includes buck turn-off circuitry configured to avoid negative inductor current by controlled switching of the tub to the higher of VIN and a second voltage. For DC-coupled configurations, boost functionality is provided by an LA boost supply, and the tub is switched to the boost supply. For AC-coupled configurations, boost functionality can be provided without boosting the LA supply rail by constraining signal peak-to-peak amplitude to be less than the LA supply voltage (maintaining a DC-average voltage on the AC-coupling capacitor), and the tub is switched to the higher of VIN and VOUT. The buck turn-off circuitry can include zero crossing detection to control M1 tub switches.

Abstract: The disclosed switched mode assisted linear (SMAL) amplifier/regulator architecture may be configured as a SMAL regulator to supply power to a dynamic load, such as an RF power amplifier. Embodiments of a SMAL regulator include configurations in which a linear amplifier and a switched mode converter (switcher) parallel coupled at a supply node, and configured such that the amplifier sets load voltage, while the amplifier and the switched mode converter are cooperatively controlled to supply load current. In one embodiment, the linear amplifier is AC coupled to the supply node, and the switched converter is configured with a capacitive charge control loop that controls the switched converter to effectively control the amplifier to provide capacitive charge control.

Abstract: A method and apparatus are provided for maximum-likelihood data detection in a partial-response (PR) data channel including a head and disk assembly providing an analog signal coupled to an analog to digital converter (ADC) providing digital samples. A plurality of digital samples are received from the ADC. The received digital samples are applied to a selected first filter and a selected second filter. The first filtered digital samples are applied to a first data detector, and the second filtered digital samples are applied to a second data detector. A predetermined parameter is identified, and at least one of the first and second data detectors is selected responsive to the identified predetermined parameter.