Patents by Inventor Kevin W. Gorman
Kevin W. Gorman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11958512Abstract: A vehicle monitoring device includes a camera or other optical sensor configured to be disposed at a trailing end of a first vehicle system. The camera or other optical sensor is configured to output one or more images or video of a field of view behind the first vehicle system. The monitoring device also includes a controller configured to receive output from one or more sensors and to activate the camera or other optical sensor to output the one or more images or video based on the output from the one or more sensors. The output from the one or more sensors indicates one or more of a change in movement of the first vehicle system, a temperature, an acoustic sound, or movement of a second vehicle system.Type: GrantFiled: September 1, 2021Date of Patent: April 16, 2024Assignee: WESTINGHOUSE AIR BRAKE TECHNOLOGIES CORPORATIONInventors: Carl L. Haas, Padam D. Swar, Danial Rice, Christopher Claussen, Joseph W. Gorman, James A. Oswald, Ann K. Grimm, Kevin Angel, James Trainor, Phillip A. Burgart, Kendrick W. Gawne, Robert Hoffman, Tim Gibson, Brian Kurz
-
Patent number: 11017873Abstract: A memory bypass circuit for a memory device comprises: a word line disable circuit; a read and write activation circuit; an internal clock generator; and a write data input circuit. The word line disable circuit is coupled to a word line of the memory device for disabling a write function to the word line. The read and write activation circuit is coupled to the memory device for reading and writing of input data. The internal clock generator is coupled to the word line disable circuit and the read/write activation circuit. The write data input circuit is coupled to a write driver of the memory device for providing write data.Type: GrantFiled: April 9, 2020Date of Patent: May 25, 2021Assignee: Synopsys, Inc.Inventors: John Edward Barth, Jr., Kevin W. Gorman, Harold Pilo
-
Publication number: 20200234784Abstract: A memory bypass circuit for a memory device comprises: a word line disable circuit; a read and write activation circuit; an internal clock generator; and a write data input circuit. The word line disable circuit is coupled to a word line of the memory device for disabling a write function to the word line. The read and write activation circuit is coupled to the memory device for reading and writing of input data. The internal clock generator is coupled to the word line disable circuit and the read/write activation circuit. The write data input circuit is coupled to a write driver of the memory device for providing write data.Type: ApplicationFiled: April 9, 2020Publication date: July 23, 2020Inventors: John Edward Barth, Jr., Kevin W. Gorman, Harold Pilo
-
Patent number: 10650906Abstract: A memory bypass circuit for a memory device comprises: a word line disable circuit; a read and write activation circuit; an internal clock generator; and a write data input circuit. The word line disable circuit is coupled to a word line of the memory device for disabling a write function to the word line. The read and write activation circuit is coupled to the memory device for reading and writing of input data. The internal clock generator is coupled to the word line disable circuit and the read/write activation circuit. The write data input circuit is coupled to a write driver of the memory device for providing write data.Type: GrantFiled: August 9, 2018Date of Patent: May 12, 2020Assignee: Synopsys, Inc.Inventors: John Edward Barth, Jr., Kevin W. Gorman, Harold Pilo
-
Patent number: 10622090Abstract: A serial arbitration for memory diagnostics and methods thereof are provided. The method includes running a built-in-self-test (BIST) on a plurality of memories in parallel. The method further includes, upon detecting a failing memory of the plurality of memories, triggering arbitration logic to shift data of the failing memory to a chip pad.Type: GrantFiled: September 28, 2018Date of Patent: April 14, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Aravindan J. Busi, Kevin W. Gorman, Deepak I. Hanagandi, Kiran K. Narayan, Michael R. Ouellette
-
Publication number: 20200051658Abstract: A memory bypass circuit for a memory device comprises: a word line disable circuit; a read and write activation circuit; an internal clock generator; and a write data input circuit. The word line disable circuit is coupled to a word line of the memory device for disabling a write function to the word line. The read and write activation circuit is coupled to the memory device for reading and writing of input data. The internal clock generator is coupled to the word line disable circuit and the read/write activation circuit. The write data input circuit is coupled to a write driver of the memory device for providing write data.Type: ApplicationFiled: August 9, 2018Publication date: February 13, 2020Inventors: John Edward Barth, JR., Kevin W. Gorman, Harold Pilo
-
Publication number: 20190035486Abstract: A serial arbitration for memory diagnostics and methods thereof are provided. The method includes running a built-in-self-test (BIST) on a plurality of memories in parallel. The method further includes, upon detecting a failing memory of the plurality of memories, triggering arbitration logic to shift data of the failing memory to a chip pad.Type: ApplicationFiled: September 28, 2018Publication date: January 31, 2019Inventors: Aravindan J. BUSI, Kevin W. GORMAN, Deepak I. HANAGANDI, Kiran K. NARAYAN, Michael R. OUELLETTE
-
Patent number: 10153055Abstract: A serial arbitration for memory diagnostics and methods thereof are provided. The method includes running a built-in-self-test (BIST) on a plurality of memories in parallel. The method further includes, upon detecting a failing memory of the plurality of memories, triggering arbitration logic to shift data of the failing memory to a chip pad.Type: GrantFiled: March 26, 2015Date of Patent: December 11, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Aravindan J. Busi, Kevin W. Gorman, Deepak I. Hanagandi, Kiran K. Narayan, Michael R. Ouellette
-
Patent number: 9946620Abstract: A memory built-in self test (“BIST”) system comprises: a controller; a single port memory engine coupled to one or more single port memories; and a non-single port memory engine coupled to one or more non-single port memories. The controller receives operation codes (“op-codes”) for testing a plurality of memory types. An output of the controller is coupled to inputs of the single port memory engine and the non-single port memory engine. The controller generates test instructions based on the received op-codes. The single port memory engine and the non-single port memory engine interpret the test instructions to test the one or more single port memories and the one or more non-single port memories.Type: GrantFiled: February 1, 2016Date of Patent: April 17, 2018Assignee: Invecas, Inc.Inventors: Kevin W. Gorman, Thomas Chadwick, Nancy Pratt
-
Patent number: 9865361Abstract: A memory diagnostic system comprises a test engine and a miscompare logic. The test engine provides test instructions with expected data to a memory under test (“MUT”). The MUT processes such test patterns and outputs the results of such test patterns as stored data. The miscompare logic has local miscompare logics and a global miscompare logic. Each of the local miscompare logics compares a predefined range of bits of the expected data with a corresponding predefined range of bits of the stored data. One or more miscompare flags are generated for one or more miscompares determined by the local miscompare logics. The global miscompare logic monitors the one or more miscompare flags. When a total number of the miscompare flags exceeds a threshold number, the global miscompare logic generates a pause signal to the local miscompare logics to capture a current state of the local miscompare logics.Type: GrantFiled: April 27, 2016Date of Patent: January 9, 2018Assignee: Invecas, Inc.Inventors: Thomas Chadwick, Kevin W. Gorman, Nancy Pratt
-
Publication number: 20170316837Abstract: A memory diagnostic system comprises a test engine and a miscompare logic. The test engine provides test instructions with expected data to a memory under test (“MUT”). The MUT processes such test patterns and outputs the results of such test patterns as stored data. The miscompare logic has local miscompare logics and a global miscompare logic. Each of the local miscompare logics compares a predefined range of bits of the expected data with a corresponding predefined range of bits of the stored data. One or more miscompare flags are generated for one or more miscompares determined by the local miscompare logics. The global miscompare logic monitors the one or more miscompare flags. When a total number of the miscompare flags exceeds a threshold number, the global miscompare logic generates a pause signal to the local miscompare logics to capture a current state of the local miscompare logics.Type: ApplicationFiled: April 27, 2016Publication date: November 2, 2017Inventors: Thomas Chadwick, Kevin W. Gorman, Nancy Pratt
-
Patent number: 9799413Abstract: A fuse controller comprises: a fuse bay, a bus, an engine, and an interface. The fuse bay stores repair and setting information for a plurality of fuse domains in a linked-list data structure. The engine manages the linked-list data structure. The engine also is coupled to the fuse domains via the bus. The interface is coupled to the engine and receives commands and data for operating the engine.Type: GrantFiled: February 1, 2016Date of Patent: October 24, 2017Assignee: Invecas, Inc.Inventors: Kevin W. Gorman, Thomas Chadwick, Nancy Pratt
-
Patent number: 9773570Abstract: Aspects of the invention provide for reducing BIST test time for a memory of an IC chip. In one embodiment, a BIST architecture for reducing BIST test time of a memory for an integrated circuit (IC) chip, the architecture comprising: a pair of latches for receiving bursts of data from a memory; a first compression stage for receiving a burst of data and compressing the burst of data into a plurality of latches; a second compression stage for comparing the compressed bursts of data with expected data; and a logic gate for determining whether there is a fail in the burst of data.Type: GrantFiled: March 6, 2013Date of Patent: September 26, 2017Assignee: International Business Machines CorporationInventors: Kevin W. Gorman, Deepak I. Hanagandi, Krishnendu Mondal, Michael R. Ouellette
-
Patent number: 9734920Abstract: Systems and methods are provided for reusing existing test structures and techniques used to test memory data to also test error correction code logic surrounding the memories. A method includes testing a memory of a computing system with an error code correction (ECC) logic block bypassed and a first data pattern applied. The method further includes testing the memory with the ECC logic block enabled and a second data pattern applied. The method also includes testing the memory with the ECC logic block enabled and the first data pattern applied.Type: GrantFiled: September 28, 2015Date of Patent: August 15, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin W. Gorman, Michael R. Ouellette, Patrick E. Perry
-
Patent number: 9514844Abstract: Logic and methods for diagnostic testing of memory and, more particularly, auto shift of failing memory diagnostics data using pattern detection are disclosed. The method includes detecting fails in the memory during a built in self test (BIST) pattern. The method further includes passing the fail information to a tester through a diagnostic pin. The method further includes pausing shift operations when it is determined that the shifting of the fail information is complete for the detected fail.Type: GrantFiled: August 26, 2014Date of Patent: December 6, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Aravindan J. Busi, Kevin W. Gorman, Kiran K. Narayan, Michael R. Ouellette
-
Patent number: 9460811Abstract: A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.Type: GrantFiled: August 7, 2014Date of Patent: October 4, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: George M. Braceras, Albert M. Chu, Kevin W. Gorman, Michael R. Ouellette, Ronald A. Piro, Daryl M. Seitzer, Rohit Shetty, Thomas W. Wyckoff
-
Publication number: 20160284426Abstract: A serial arbitration for memory diagnostics and methods thereof are provided. The method includes running a built-in-self-test (BIST) on a plurality of memories in parallel. The method further includes, upon detecting a failing memory of the plurality of memories, triggering arbitration logic to shift data of the failing memory to a chip pad.Type: ApplicationFiled: March 26, 2015Publication date: September 29, 2016Inventors: Aravindan J. BUSI, Kevin W. GORMAN, Deepak I. HANAGANDI, Kiran K. NARAYAN, Michael R. OUELLETTE
-
Publication number: 20160224450Abstract: A memory built-in self test (“BIST”) system comprises: a controller; a single port memory engine coupled to one or more single port memories; and a non-single port memory engine coupled to one or more non-single port memories. The controller receives operation codes (“op-codes”) for testing a plurality of memory types. An output of the controller is coupled to inputs of the single port memory engine and the non-single port memory engine. The controller generates test instructions based on the received op-codes. The single port memory engine and the non-single port memory engine interpret the test instructions to test the one or more single port memories and the one or more non-single port memories.Type: ApplicationFiled: February 1, 2016Publication date: August 4, 2016Inventors: Kevin W. Gorman, Thomas Chadwick, Nancy Pratt
-
Publication number: 20160224451Abstract: A fuse controller comprises: a fuse bay, a bus, an engine, and an interface. The fuse bay stores repair and setting information for a plurality of fuse domains in a linked-list data structure. The engine manages the linked-list data structure. The engine also is coupled to the fuse domains via the bus. The interface is coupled to the engine and receives commands and data for operating the engine.Type: ApplicationFiled: February 1, 2016Publication date: August 4, 2016Inventors: Kevin W. Gorman, Thomas Chadwick, Nancy Pratt
-
Publication number: 20160064102Abstract: Logic and methods for diagnostic testing of memory and, more particularly, auto shift of failing memory diagnostics data using pattern detection are disclosed. The method includes detecting fails in the memory during a built in self test (BIST) pattern. The method further includes passing the fail information to a tester through a diagnostic pin. The method further includes pausing shift operations when it is determined that the shifting of the fail information is complete for the detected fail.Type: ApplicationFiled: August 26, 2014Publication date: March 3, 2016Inventors: Aravindan J. BUSI, Kevin W. GORMAN, Kiran K. NARAYAN, Michael R. OUELLETTE