Abstract: Storage protection keys and system data share the same physical storage. The key region is dynamically relocatable by firmware. A Configuration Array is used to map the absolute address of the key region in to its physical address. The absolute address of keys can be fixed even though the physical location of the keys is relocated into a different region. A triple-detect double correct ECC scheme is used to protect keys. The ECC scheme is different from regular data in the storage and can be used to detect illegal access. Extra firmware and hardware is also designed to restrain customer's applications from directly accessing keys. With the key region being relocatable, the firmware could move the key region away from a known faulty area in a memory to improve system RAS. We also achieved the commonality objective that key memory device can use the same memory devices with other server systems that do not use keys.

Abstract: A DDR SDRAM DIMM for a mainframe main storage subsystem has a plurality of DDR SDRAMs on a rectangular printed circuit board having a first side and a second side, a length (152 MM=6 inch) between 149 and 153 millimeters and optimized at 149.15 mm or 151.35 mm in length and first and second ends having a width smaller than the length; a first plurality of connector locations on the first side extending along a first edge of the board that extends the length of the board, a second plurality of connector locations of the second side extending on the first edge of the board, a locating key having its center positioned on the first edge and located between 80 mm and 86 mm and optimized with a locating key 1.5 mm wide centered at 81.58 or 85.67 mm from the first end of the board and located between 64 and 70 mm and optimized with the locating key centered at 67.58 or 65.675 from the second end of the board.

Abstract: A memory subsystem with positional read data latency that includes one or more memory modules, a memory controller and one or more memory busses is provided. The memory controller includes instructions for providing positional read data latency. The memory modules and the memory controller are interconnected via the memory busses.

Abstract: A memory subsystem that includes segment level sparing. The memory subsystem includes a cascaded interconnect system with segment level sparing. The cascaded interconnect system includes two or more memory assemblies and a memory bus. The memory bus includes multiple segments and the memory assemblies are interconnected via the memory bus.

Abstract: A memory subsystem with positional read data latency that includes a cascaded interconnect system with one or more memory modules, a memory controller and one or more memory busses. The memory controller includes instructions for providing positional read data latency. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the memory busses.

Abstract: A self test function in the Memory Controller is utilized to generate unique and continuous data patterns for each of the words which are stored into two consecutive DRAM addresses in two spaced store operations. The self test function then generates fetch commands to read back the unique data patterns from the two DRAM addresses. In the fetch operations, the data transmission for each operation and between both operations is contiguous (no gaps). A self test data comparison function is then used to compare these fetched data words to data patterns which are generated from the self test data generator. Bit error counters from the memory controller keeps track of any miscompares. By reading out a unique signature from these bit counters, it can be determined whether the store path data are misaligned early or late or correct and/or the fetch path data are misaligned early or late or correct. In addition, the exact number of cycles the data are early or late is known.

Abstract: A DDR SDRAM DIMM for a mainframe main storage subsystem has a plurality of DDR SDRAMs on a rectangular printed circuit board having a first side and a second side, a length (152 MM=6 inch) between 149 and 153 millimeters and optimized at 149.15 mm or 151.35 mm in length and first and second ends having a width smaller than the length; a first plurality of connector locations on the first side extending along a first edge of the board that extends the length of the board, a second plurality of connector locations of the second side extending on the first edge of the board, a locating key having its center positioned on the first edge and located between 80 mm and 86 mm and optimized with a locating key 1.5 mm wide centered at 81.58 or 85.67 mm from the first end of the board and located between 64 and 70 mm and optimized with the locating key centered at 67.58 or 65.675 from the second end of the board.

Abstract: Storage protection keys and system data share the same physical storage. The key region is dynamically relocatable by firmware. A Configuration Array is used to map the absolute address of the key region in to its physical address. The absolute address of keys can be fixed even though the physical location of the keys is relocated into a different region. A triple-etect double correct ECC scheme is used to protect keys. The ECC scheme is different from regular data in the storage and can be used to detect illegal access. Extra firmware and hardware is also designed to restrain customer's applications from directly accessing keys. With the key region being relocatable, the firmware could move the key region away from a known faulty area in a memory to improve system RAS. We also achieved the commonality objective that key memory device can use the same memory devices with other server systems that do not use keys.

Abstract: A method of regulating power for multi-node computer system components has a closed-ring path that links all the power governors and circulating in the ring is a system power number that represents the power consumption of the entire system. Meanwhile, all the governors keep counting its local power consumption. Each time the number passes a governor, the governor will add its local count onto this number, store this number for future usage, and reset its local count. When the new number returns back to the same power governor, the governor will subtract the new number with its stored number to calculate the overall system power usage within a number circulation period. The system power number overflow problem is also detected with a counter if the incoming number is smaller then the number previously stored. The counter whose counting capacity is greater than the maximum system power usage on all the nodes within a number circulation period.

Abstract: A power governor for DRAM in a multi-node computer system regulating memory power consumption of an entire computer system employs a closed ring that connects all the power governors within the system to enable them to work in concert so that each of the power governors has the knowledge of memory activities within the entire system. They then control and limit the memory usage based on a true overall measurement instead of just local measurement. Each nodal power governor has memory command counter, ring number receiver, ring number transmitter, governor activation controller, and memory traffic controller. Each nodal power governor counts the weight of memory command. The degree of limiting actual memory activities can be programmed when the governor is active. Besides, the command priorities can be adjusted in activation too. A hybrid ring structure can be employed with a nodal power structure to achieve the fastest number circulation speed economically.

Abstract: Disclosed are a concurrent selftest engine and its applications to verify, initialize and scramble the system memory concurrently along with mainline operations. In prior art, memory reconfiguration and initialization can only be done by firmware with a full system shutdown and reboot. The disclosed hardware, working along with firmware, allows us to do comprehensive memory test operations on the extended customer memory area while the customer mainline memory accesses arc running in parallel. The hardware consists of concurrent selftest engines and priority logic. Great flexibility is achieved by the new design because customer-usable memory area can be dynamically allocated, verified and initialized. The system performance is improved by the fact that the selftest is hardware-driven whereas in prior art, the firmware drove the selftest. More comprehensive test patterns can be used to improve system memory RAS as well.

Abstract: A packetized cascade memory system including a plurality of memory assemblies, a memory bus including multiple segments, a bus repeater module and a segment level sparing module. The bus repeater module is in communication with two or more of the memory assemblies via the memory bus. The segment level sparing module provides segment level sparing for the communication bus upon segment failure.

Abstract: Memory is scrubbed by an improved non-linear method giving scrubbing preference to the central storage region having the characteristic of a high risk read-only memory such as the CPA region to prevent the accumulation of temporary data errors. The chip row on which the CPA resides is scrubbed after each time the scrubbing of a non-CPA chip row in a PMA completed successfully. The next non-CPA least recently scrubbed chip row would be selected for scrubbing after scrubbing completed on the CPA chip row. This in a first case provides non-linear selection methods of scrubbing central storage of computer systems to more frequently select (“select” herein encompasses the meaning of “favor”) scrub regions having the characteristic of a predominately read-only memory making those regions at a higher risk of failure than those regions having lower risk because of frequent write operations.

Abstract: A computer system enabling dynamic sparing employs a standby component which is identical to three other additional components and which operates like these other three active components while the computer system is running. Any one of these three other active components can be spared out dynamically in the computer system while it is running using a result of voting scheme and connecting of these four components in such a way that the system can dynamically spare while the system is still in operation. Such dynamic sparing gives the system a better reliability and availability when compared to today's computer system.

Abstract: Disclosed is a method and a computer circuit design for a dynamic clock ratio detector. The detector is used to determine the ratio between two clock domains. The detector has a driver 101 and a receiver, which reside in different clock domains. The driver 101 constantly produces a ratio clock pulse to the receiver. The ratio-counter in the receiver counts the pulse width based on its local clock cycles. The clock ratio detector has many features, including absorbing the meta-stability effect when the pulse crosses an asynchronous interface. The clock ratio detector prevents output counts oscillation, provides an adjustable ratio-detecting coverage range, a programmable system-parameter generator 104, and a programmable error reporter 105.

Abstract: A computer system enabling dynamic sparing employs a standby component which is identical to three other additional components and which operates like these other three active components while the computer system is running. Any one of these three other active components can be spared out dynamically in the computer system while it is running using a result of voting scheme and connecting of these four components in such a way that the system can dynamically spare while the system is still in operation. Such dynamic sparing gives the system a better reliability and availability when compared to today's computer system.

Abstract: Disclosed is a method and a computer circuit design for a dynamic clock ratio detector. The detector is used to determine the ratio between two clock domains. The detector has a driver 101 and a receiver, which reside in different clock domains. The driver 101 constantly produces a ratio clock pulse to the receiver. The ratio-counter in the receiver counts the pulse width based on its local clock cycles. The clock ratio detector has many features, including absorbing the meta-stability effect when the pulse crosses an asynchronous interface. The clock ratio detector prevents output counts oscillation, provides an adjustable ratio-detecting coverage range, a programmable system-parameter generator 104, and a programmable error reporter 105.

Abstract: In a computer RAM memory system, the memory is subjected to a self test operation during which data is written to and read out from each address location of the memory. The data read out is compared with the written data to detect errors and the number of errors at each bit position is counted. When the number of errors in a bit position-exceeds a selected threshold, the corresponding DRAM is replaced by a spare DRAM. When the self test detects two or more errors in the same double word, the DRAM corresponding to the bit position having the highest error count is replaced with a spare DRAM. The memory is periodically scrubbed and errors detected during the scrubbing operation are counted for each bit position. At the end of the scrubbing of a chip row the DRAMs corresponding to bit positions at which the error counts exceed a selected threshold are replaced with spare DRAMs. When a multiple bit error in a double word is detected during scrubbing, the corresponding double word is tagged.

Abstract: A memory interface between the storage controller and memory card of an S/390 system uses the S/390 Storage Protect (SP) Key as an indication or protocol of storage command acceptance by the memory card. When the SP key is returned, then the command is deemed to be accepted by the memory card and the key will be used by the processor for its storage validation in accordance with the S/390 architecture. In the event that the memory card detected an error associated with the command, it will then return an error response code via a memory status bus. The memory status bus is multiplexed to service the existing architected requirement as well as an indicator of handshaking between the memory controller and the memory card.

Abstract: A memory request protocol allows a memory request to be withdrawn or "cancelled" without penalty so no memory resource is wasted in doing so during an assigned "cancel window". When the memory card starts to process a command from the memory controller, for a predefined number of cycles a period of time is available where the memory card can't accept another command due to a resource conflict. This provides an opportunity to re-balance requests to the memory controller in this period of time or "cancel window".