Abstract: A method and a layered planar heterostructure comprising one of or both n and p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate wherein one layer is silicon or silicon germanium under tensile strain and one layer is silicon germanium under compressive strain whereby n channel field effect transistors may be formed with a silicon or silicon germanium layer under tension and p-channel field effect transistors may be formed with a silicon germanium layer under compression. The plurality of layers may be common to both subsequently formed p and n-channel field effect transistors which may be interconnected to form CMOS circuits. The invention overcomes the problem of forming separate and different layered structures for p and n-channel field effect transistors for CMOS circuitry on ULSI chips.

Abstract: This invention is a three layer Si.sub.x Ge.sub.1-x structure formed on a silicon substrate in which a thin, lightly doped Si.sub.x Ge.sub.1-x layer is formed between two heavily doped Si.sub.x Ge.sub.1-x layers. The incorporation of at least 10% germanium in the silicon provides for intervalley scattering of carriers in the conduction band of the Si.sub.x Ge.sub.1-x layers. This intervalley scattering leads to the negative differential conductance necessary for transferred electron device (TED) operation. Additionally, the lightly doped Si.sub.x Ge.sub.1-x layer is made very thin, on the order of 2,000 to 7,000 Angstroms, and the current flow through the this layer is vertical so that a high electric field can be placed across the lightly doped layer without applying a high voltage across the lightly doped layer. The lightly doped layer can be made thin even though it is interposed between two heavily doped layers because the growth of the in-situ doped Si.sub.x Ge.sub.