Abstract: Systems and methods are presented for secured communications in a controller area network for a vehicle system. A first electronic processor is communicatively coupled to a memory and configured to operate one or more vehicle systems. A second electronic processor is configured to generate message authentication codes to verify data communications between the first electronic processor and at least one other vehicle system controller in the controller area network. The direct memory access (DMA) module is configured to facilitate direct communications between the second electronic processor and the memory so that the first electronic processor can continue to execute other instructions while message authentication codes are generated by the second electronic processor for incoming and outgoing message data.

Abstract: Systems and methods are presented for secured communications in a controller area network for a vehicle system. A first electronic processor is communicatively coupled to a memory and configured to operate one or more vehicle systems. A second electronic processor is configured to generate message authentication codes to verify data communications between the first electronic processor and at least one other vehicle system controller in the controller area network. The direct memory access (DMA) module is configured to facilitate direct communications between the second electronic processor and the memory so that the first electronic processor can continue to execute other instructions while message authentication codes are generated by the second electronic processor for incoming and outgoing message data.

Abstract: A fast lock/self-tuning VCO based PLL integrated circuit (10) adapted for implementation in wireless communication systems requiring a high transfer data rate. The present invention is preferably implemented using and RFSiGe or a CMOS process in a WDCMA chipset, and can be used in other systems such as GSM and EDGE. The present invention utilizes the content of a divider (24) as a monitor of the lock condition of the PLL (10), permitting the fast-tuning of the VCO (14) to almost the final frequency using a controller (22) and a coarse DAC (20).