Abstract: A multiple output current mirror of improved accuracy suitable for use in a multi-level memory or analog applications is described. A reference current is mirrored in number of branches to produce replicas of the original current without degrading the original current. Both the mirrored transistor, through which the original current flows, and the mirroring transistors, which provide the replicated currents in each of the branches, are subdivided into a number of separate transistors. The effective channel width of a corresponding original transistor is shared among the transistors forming its subdivision. These subdivided elements are then physically arranged into a number partial current mirrors whose outputs are combined to form the total current mirror.

Abstract: A multiple output current mirror of improved accuracy suitable for use in a multi-level memory or analog applications is described. A reference current is mirrored in number of branches to produce replicas of the original current without degrading the original current. Both the mirrored transistor, through which the original current flows, and the mirroring transistors, which provide the replicated currents in each of the branches, are subdivided into a number of separate transistors. The effective channel width of a corresponding original transistor is shared among the transistors forming its subdivision. These subdivided elements are then physically arranged into a number partial current mirrors whose outputs are combined to form the total current mirror.

Abstract: The present invention reduces the demand on the number of pins of an EEPROM memory chip or flash EEPROM chip by multiplexing a subset of the pins between the high voltage generator circuit of the chip and the chip select circuit. When the chip receives an enable signal, the subset of pins are connected to the chip's charge pump circuit allowing it to be connected to an external set of capacitors through these pins. When the enable signal is de-asserted, the subset of pins are connected to the chip select circuit. When the chip is part of an array of chips, this allows this subset of pins to be used to assign a chip address for determining the chips position in the array. When a number of chips are placed in an array, one (or more) of the chips supplies the other chips in the array with the high voltage and current needed for erasing and programming. To be able to do this, this chip is enabled and connected through the subset of pins to the external capacitors.

Abstract: A port expander for providing an external memory to be used with a microcontroller but recapturing the use of I/O ports which are lost due to the coupling of the memory. Two ports are coupled to the microcontroller for transfer of address and data information. An EPROM in the port expander provides the external memory while a special function register is used to couple data to and from two I/O ports. A configuration register provides programmability of which address values address the memory and which address values address the special function registers.

Abstract: A test mode enable circuit in which a test mode code is written to one latch and a test mode enable code is written to a second latch. The test mode enable code is compared to preprogrammed values stored in the enable circuit. When the test mode enable code matches the preprogrammed value, a presence of a high voltage activates a test mode enable signal for entering the test mode. The latched test mode code is then used to perform the desired test. Additionally a pulsewidth detector is used as a filter to permit only high voltages of a minimum pulsewidth duration to activate the enable signal thereby preventing false triggering.

Abstract: A CMOS output driver includes an n-channel low threshold device in series between a p-channel transistor and an output terminal. Under normal driver operation, the low threshold transistor drops essentially zero volts and is imperceptible in the circuit. However, under special mode conditions when high voltage is applied to the output terminal, the low threshold transistor stops conducting when the output terminal approaches Vcc, so that any further increase in the voltage at the output terminal cannot be applied to the drain of the p-channel transistor which can cause its failure.