Abstract: An amplifier module has a substrate, as assembly having one or more integrated circuit (IC) dies mounted to the substrate, and one or more other electronic components mounted to the substrate. The assembly receives an input signal and generates an amplified output signal. The one or more other electronic components perform one or more amplifier-related functions. The amplifier module is adapted to be mounted to a circuit board (CB) as a distinct electronic package. The invention may be implemented as an electronic system having the CB and at least one such amplifier module mounted to the CB.

Abstract: A drive circuit for a MEMS device, an integrated circuit having a plurality of MEMS devices and drivers, a method of operating the drive circuit and a method of manufacturing the integrated circuit. In one embodiment, the drive circuit includes: (1) an electrode driver and (2) a switching network, coupled to an output of said electrode driver that: (a) in a first configuration, couples said output to a first electrode of an axis of said MEMS device and grounds an opposing second electrode of said axis of said MEMS device and (b) in a second configuration, couples said output to said second electrode and grounds said first electrode.

Abstract: A drive circuit for a MEMS device, an integrated circuit having a plurality of MEMS devices and drivers, a method of operating the drive circuit and a method of manufacturing the integrated circuit. In one embodiment, the drive circuit includes: (1) an electrode driver and (2) a switching network, coupled to an output of said electrode driver that: (a) in a first configuration, couples said output to a first electrode of an axis of said MEMS device and grounds an opposing second electrode of said axis of said MEMS device and (b) in a second configuration, couples said output to said second electrode and grounds said first electrode.

Abstract: A data communication method and apparatus includes an integral bit error rate test system. The system is adapted to receive digital data signals to be transmitted over a communication link and includes a transmitter for transmitting the data signals onto the link. A test signal pattern generator generates a determinable pattern of digital bit test signals which are insertable into an input of the transmitter in place of the digital data signals. A receiver is coupled to the link for receiving the bit test signals and for comparing the received pattern of the bit test signals to the determinable pattern. The bit error rate is computed from the number of bit differences between the transmitted test signals and the determinable pattern.

Abstract: An arrangement is disclosed for determining a byte error rate (ByER) of a received digital signal. In particular, a local byte clock signal is generated and a complement of the received signal (or clock signal) is compared to the clock signal (or received signal). When both are the same logic value, as determined by a series of logic gates, an error is deemed to have occurred. A counter is utilized to track a number of occurrences N over a predetermined period of time T.

Abstract: A method is disclosed for determining the byte error rate (ByER) of a received digital signal. In particular, a local byte clock signal is generated and a complement of the received signal (or clock signal) is compared to the clock signal (or received signal). When both are the same logic value, as determined by a series of logic gates, an error is deemed to have occurred. The total number of errors N over a predetermined period of time T are then counted.