Abstract: A system and method for treating congestive heart failure in a patient, including: implanting at least one pressure sensor in a desired location within the patient; providing an ex-vivo interrogation system and monitoring system that can be configured to optionally affect at least one of: selectively energizing the at one pressure sensor, receiving a return or output signal from the at one pressure sensor, processing the return signal, and displaying processed data derived from the at least one pressure sensor to a physician. The system and method also includes deriving diagnostic and treatment information from the processed data and sending diagnostic and treatment information to the patient.

Abstract: A differential data sampling circuit is provided for sampling an input signal line with precise timing so as to provide reduced sensitivity to noise. The differential data sampling circuit includes a latch circuit for initially sampling a differential data signal in response to a first strobe signal. The latch circuit operates to rapidly capture the signal level present on the input signal line. The output of the latch circuit is then sampled by a strobe circuit in order to capture and hold the output of the latch circuit based on a second strobe signal. In preferred embodiments, the latch circuit has a high input impedance. A digital data receiver including such a differential data sampling circuit is also provided.

Abstract: An analog-to-digital converter (ADC) (112) for sampling high speed video signals includes Pre-amplifiers (502, 504, 506) electrically coupled to Post-amplifiers (508, 510, 512) that are electrically coupled to output latches (514, 517, 519, 521, 523, 525, and 527). A sampling clock signal (116) clocks the output latches (514, 517, 519, 521, 523, 525, and 527) to sample an input analog electronic signal to provide a digital representation thereof. The ADC (112) includes an auto-zeroing function to cancel bias voltages at the Post-amplifiers (508, 510, 512) during a video signal horizontal blanking time period. The ADC (112) includes a bit dithering function by alternating sets of reference voltages into the Pre-amplifiers (502, 504, 506) increasing bit resolution. The ADC (112) includes wired interconnect interpolation between the Pre-amplifiers (502, 504, 506) and Post-amplifiers (508, 510, 512) and between the Post-amplifiers (508, 510, 512) and the output latches (514, 517, 519, 521, 523, 525, and 527).