Patents by Inventor Khoi A. Phan
Khoi A. Phan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6954678Abstract: A system and method facilitating lithography defect solution generation is provided. The invention includes a defect solution component and a defect alert component. The defect solution component provides potential solution(s) to a defect within the lithography process utilizing artificial intelligence technique(s) (e.g., Bayesian learning methods that perform analysis over alternative dependent structures and apply a score, Bayesian classifiers and other statistical classifiers, including decision tree learning methods, support vector machines, linear and non-linear regression and/or neural network).Type: GrantFiled: September 30, 2002Date of Patent: October 11, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Khoi A. Phan, Bhanwar Singh, Bharath Rangarajan, Ramkumar Subramanian
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Publication number: 20050193362Abstract: A system facilitating measurement and correction of overlay between multiple layers of a wafer is disclosed. The system comprises an overlay target that represents overlay between three or more layers of a wafer and a measurement component that determines overlay error existent in the overlay target, thereby determining overlay error between the three or more layers of the wafer. A control component can be provided to correct overlay error between adjacent and non-adjacent layers, wherein the correction is based at least in part on measurements obtained by the measurement component.Type: ApplicationFiled: March 1, 2004Publication date: September 1, 2005Inventors: Khoi Phan, Bharath Rangarajan, Bhanwar Singh
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Patent number: 6924157Abstract: One aspect of the present invention relates to a system and method for controlling defect formation during a resist strip process. The system includes a reaction chamber comprising a patterned resist layer overlying a semiconductor structure wherein the resist layer is being exposed to a plasma material flowing into the chamber in order to facilitate removing the resist layer from the structure, a plasma-resist particle monitoring system connected to the reaction chamber and programmed to determine a particle count in the reaction chamber during the resist strip process, and a reaction controller coupled to the chamber and to the monitoring system, the reaction controller being programmed to receive particle data from the monitoring system to facilitate determining whether the counted particles in the chamber are within a tolerable limit. The method involves continuing to expose the structure and the chamber to the plasma until an acceptable particle count is obtained.Type: GrantFiled: October 21, 2002Date of Patent: August 2, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Khoi A. Phan, Bhanwar Singh, Bharath Rangarajan
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Patent number: 6915177Abstract: The present invention provides systems and methods that facilitate performing fabrication process. Critical parameters are valued collectively as a quality matrix, which weights respective parameters according to their importance to one or more design goals. The critical parameters are weighted by coefficients according to information such as, product design, simulation, test results, yield data, electrical data and the like. The invention then can develop a quality index which is a composite “score” of the current fabrication process. A control system can then do comparisons of the quality index with design specifications in order to determine if the current fabrication process is acceptable. If the process is unacceptable, test parameters can be modified for ongoing processes and the process can be re-worked and re-performed for completed processes. As such, respective layers of a device can be customized for different specifications and quality index depending on product designs and yields.Type: GrantFiled: September 30, 2002Date of Patent: July 5, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Khoi A. Phan, Bhanwar Singh, Bharath Rangarajan, Ramkumar Subramanian
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Publication number: 20050048741Abstract: The present invention relates to inspection methods and systems utilized to provide a best means for inspection of a wafer. The methods and systems include wafer-to-reticle alignment, layer-to-layer alignment and wafer surface feature inspection. The wafer-to-reticle alignment is improved by the addition of diagonal lines to existing alignment marks to decrease the intersection size and corresponding area that a desired point can reside. Layer-to-layer alignment is improved in a similar manner by the addition of oblique and/or non-linear line segments to existing overlay targets. Also, providing for wafer surface inspection in a multitude of desired diagonal axes allows for more accurate feature measurement.Type: ApplicationFiled: September 2, 2003Publication date: March 3, 2005Inventors: Khoi Phan, Bharath Rangarajan, Bhanwar Singh
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Patent number: 6844206Abstract: A system and/or method are disclosed for measuring and/or controlling refractive index (n) and/or lithographic constant (k) of an immersion medium utilized in connection with immersion lithography. A known grating structure is built upon a substrate. A refractive index monitoring component facilitates measuring and/or controlling the immersion medium by utilizing detected light scattered from the known grating structure.Type: GrantFiled: August 21, 2003Date of Patent: January 18, 2005Assignee: Advanced Micro Devices, LLPInventors: Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh, Ramkumar Subramanian
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Patent number: 6818360Abstract: A system that monitors and controls a phase shift mask fabrication process is disclosed. Acoustic beams and/or beams of light are selectively directed at portions of the mask to scan the mask as it matriculates through the fabrication process. Portions of the beams that pass through and/or are reflected from the mask are collected and examined, such as in accordance with scatterometry based techniques, to determine, for example, whether cracks or other defects are forming on or within the mask, and/or whether features, such as apertures, are being formed as desired. The measurements can be employed to generate feed forward and/or feedback control data that can utilized to selectively adjust one or more fabrication components and/or operating parameters associated therewith to adapt the fabrication process. Controlling the mask fabrication process facilitates improved mask fabrication and resulting chip quality as compared to conventional systems.Type: GrantFiled: September 30, 2002Date of Patent: November 16, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Khoi A. Phan, Bhanwar Singh, Bharath Rangarajan
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Patent number: 6809793Abstract: A system and method are disclosed which enable temperature of a substrate, such as mask or reticle, to be monitored and/or regulated. One or more temperature sensors are associated with the substrate to sense substrate temperature during exposure by an exposing source. The sensed temperature is used to control one or more process parameters of the exposure to help maintain the substrate at or below a desired temperature.Type: GrantFiled: January 16, 2002Date of Patent: October 26, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Khoi A. Phan, Bhanwar Singh, Ramkumar Subramanian, Bharath Rangarajan
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Patent number: 6808591Abstract: A systems and methodologies are provided for metal overetch control. Metal overetch processes are controlled by utilizing overetch device models to determine overetch times or overetch endpoints. The systems and methodologies reduce the need for manual testing and manual overetch characterization. An overetch system includes a metal etcher, a target device and an overetch controller. The target device is located in or on the metal etcher. The overetch controller is coupled to the metal etcher. The overetch controller controls overetching of the target device by the metal etcher. The overetch controller includes an overetch time controller, a set of etch control models and a control system.Type: GrantFiled: December 12, 2001Date of Patent: October 26, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Khoi A. Phan, Bharath Rangarajan, Christopher F. Lyons, Steven C. Avanzino, Ramkumar Subramanian, Bhanwar Singh, Cyrus E. Tabery
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Patent number: 6784446Abstract: One aspect of the present invention relates to a system and method for detecting defects on a reticle by inspecting latent images printed on a resist wafer by the reticle. The system includes a wafer having a printed photoresist layer formed thereon, a latent image inspection system connected to the wafer exposure system for examining the printed photoresist layer in order to determine whether a reticle employed to print the photoresist layer is defective, and a processor for receiving data from the inspection system in order to verify the presence of defects on the reticle. The method involves printing a first latent image, a second latent image, and a third latent image on a resist wafer using a reticle, and comparing the three latent images to one another to determine whether the reticle is defective. Comparison of the latent images may be facilitated by employing an optical system programmed to perform such comparisons.Type: GrantFiled: August 29, 2002Date of Patent: August 31, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Khoi A. Phan, Bhanwar Singh, Bharath Rangarajan
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Patent number: 6771356Abstract: A system for monitoring a fabrication process is provided. The system includes one or more light sources, each light source directing light to one or more gratings on a wafer. Light reflected from the gratings is collected by a measuring system that processes the collected light. The collected light is indicative of distortion due to stress at respective portions of the wafer. The measuring system provides distortion/stress related data to a processor that determines the acceptability of the distortion of the respective portions of the wafer. The collected light may be analyzed by scatterometry systems to produce scatterometry signatures associated with distortion and to produce feed-forward control information that can be employed to control semiconductor fabrication processes.Type: GrantFiled: January 16, 2002Date of Patent: August 3, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Christopher F. Lyons, Bhanwar Singh, Steven C. Avanzino, Khoi A. Phan, Bharath Rangarajan, Ramkumar Subramanian, Cyrus E. Tabery
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Patent number: 6762133Abstract: The present invention relates to systems and methods for mitigating pattern collapse in ultra-thin resist processing. In one embodiment, the present invention relates to etching extremely fine patterns into a hardmask immediately after developing an ultra-thin resist, wherein the resist is not dried.Type: GrantFiled: July 23, 2001Date of Patent: July 13, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Bharath Rangarajan, Ramkumar Subramanian, Khoi A. Phan
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Patent number: 6759179Abstract: Methods and systems are disclosed for reducing resist residue defects in a semiconductor manufacturing process. The methods comprise appropriate adjustment of hardware, substrate, resist, developer, and process variables in order to remove resist residues from a semiconductor substrate structure in order to reduce resist residue defects therein, including special vapor prime and development operations.Type: GrantFiled: January 16, 2002Date of Patent: July 6, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Khoi A. Phan, Jeffrey Erhardt, Jerry Cheng, Richard J. Bartlett, Anthony P. Coniglio, Wolfram Grundke, Carol M. Bradway, Daniel E. Sutton, Martin Mazur
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Patent number: 6753261Abstract: One aspect of the present invention relates to a system and method for monitoring in-situ a chemical composition at or near a surface of a wafer during plasma etch to detect defects The method involves the steps of providing a semiconductor substrate comprising at least one top layer, wherein the semiconductor substrate comprises at least one chemical-containing contaminant; subjecting the semiconductor substrate to a plasma etch process, whereby at least a portion of the top layer is removed; during the plasma etch process, detecting for a presence of the chemical-containing contaminant using one of an Auger Electron Spectroscopy system or Energy Dispersive X-ray Analysis system; and if present, determining whether the presence of the chemical-containing contaminant exceeds a threshold limit.Type: GrantFiled: January 17, 2002Date of Patent: June 22, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Khoi A. Phan, Arvind Halliyal, Bhanwar Singh
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Patent number: 6741445Abstract: A system and methodology is provided for monitoring and controlling static charge during wafer and mask fabrication. The static charge on a target device is monitored. If the static charge becomes too high, corrective actions are taken to reduce the static charge. An antistatic solution is dispensed on the target device. The system and methodology provided reduce damage resulting from electrostatic discharge during fabrication. The system and methodology also reduce delays during fabrication by automatically controlling static charge without the need for manual intervention.Type: GrantFiled: January 16, 2002Date of Patent: May 25, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Khoi A. Phan, Bhanwar Singh, Bharath Rangarajan, Ramkumar Subramanian
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Patent number: 6724476Abstract: One aspect of the present invention relates to a system and method of monitoring for defects on a wafer before and after forming a photoresist layer on the wafer. The system includes a device fabrication system comprising one or more wafer processing system components for producing a device; a defect metrology system integrated within and on track with the fabrication system operative to inspect the wafer for defects before it proceeds to photoresist processing; and a wafer cleaning system for reducing an amount of defects detected on the front and/or back side of the wafer. If the amount of defects have been sufficiently reduced, the front side of the wafer may be coated with a photoresist. Subsequently, the back side of the wafer may be inspected and cleaned while protecting the front side from damage. Cleaning of the wafer may be performed with a thermal shock treatment, for example.Type: GrantFiled: October 1, 2002Date of Patent: April 20, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Khoi A. Phan, Bhanwar Singh, Bharath Rangarajan
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Publication number: 20040063009Abstract: The present invention provides systems and methods that facilitate performing fabrication process. Critical parameters are valued collectively as a quality matrix, which weights respective parameters according to their importance to one or more design goals. The critical parameters are weighted by coefficients according to information such as, product design, simulation, test results, yield data, electrical data and the like. The invention then can develop a quality index which is a composite “score” of the current fabrication process. A control system can then do comparisons of the quality index with design specifications in order to determine if the current fabrication process is acceptable. If the process is unacceptable, test parameters can be modified for ongoing processes and the process can be re-worked and re-performed for completed processes. As such, respective layers of a device can be customized for different specifications and quality index depending on product designs and yields.Type: ApplicationFiled: September 30, 2002Publication date: April 1, 2004Inventors: Khoi A. Phan, Bhanwar Singh, Bharath Rangarajan, Ramkumar Subramanian
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Sensor to predict void free films using various grating structures and characterize fill performance
Patent number: 6684172Abstract: One aspect of the invention relates to a metal fill process and systems therefor involving providing a standard calibration wafer having a plurality of fill features of known dimensions in a metalization tool; depositing a metal material over the standard calibration wafer; monitoring the deposition of metal material using a sensor system, the sensor system operable to measure one or more fill process parameters and to generate fill process data; controlling the deposition of metal material to minimize void formation using a control system wherein the control system receives fill process data from the sensor system and analyzes the fill process data to generate a feed-forward control data operative to control the metalization tool; and depositing metal material over a production wafer in the metalization tool using the fill process data generated by the sensor system and the control system. The invention further relates to tool characterization processes and systems therefor.Type: GrantFiled: December 27, 2001Date of Patent: January 27, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Ramkumar Subramanian, Steven C. Avanzino, Christopher F. Lyons, Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh, Cyrus E. Tabery -
Patent number: 6665065Abstract: A system and method are provided for detecting latent defects in a mask or reticle, which defects may vary as a function of radiation at exposure wavelengths. By way of example, the mask or reticle is inspected, exposed to radiation at a specified wavelength, and then reinspected. A correlation between the inspection results before and after exposure provides an indication of exposure-related defects, which may include defect growth and/or formation of defects caused by the exposure. By way of further illustration, the combination of inspection and exposure of a mask or reticle may be implemented with respect to a pellicized mask or reticle so as to detect additional defects related to use of the pellicle with the mask or reticle.Type: GrantFiled: April 9, 2001Date of Patent: December 16, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Khoi A. Phan, Bhanwar Singh, Wolfram Porsche
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Patent number: 6663723Abstract: One aspect of the present invention relates to a method of cleaning a patterned photoresist clad structure involving the steps of contacting the patterned photoresist clad structure with an alcohol vapor comprising at least one compound having the Formula ROH, wherein R is a hydrocarbon group comprising from 4 to about 8 carbon atoms; condensing the alcohol vapor on the patterned photoresist clad structure; and removing the condensed alcohol vapor from the patterned photoresist clad structure. Another aspect of the present invention involves the use of an alcohol vapor having a boiling point from about 102° C. to about 175° C. Yet another aspect of the present invention involves the use of an alcohol vapor having a flash point from about 15° C. to about 80° C.Type: GrantFiled: October 10, 2001Date of Patent: December 16, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Michael K. Templeton, Ramkumar Subramanian, Khoi A. Phan, Bharath Rangarajan