Abstract: An integrated circuit comprising a plurality of metal programmable revision identification (MPRI) cells, wherein each MPRI cell further comprises a plurality of metal layers, a plurality of vias and an output.

Abstract: An optical logic circuit is disclosed. The optical logic circuit is configured on a substrate of a first material. The optical logic circuit also has an optical layer which overlays the substrate layer and is at least partially configured of a second material. The optical layer is patterned to provide a plurality of optical pathways. At least one of the optical pathways transmits an optical bias and at least one optical pathway is configured to provide an optical input and at least one optical pathway is configured to provide an optical output. The optical pathways are configured to provide a Boolean logic output based on the at least one optical input.

Abstract: A system and method for routing power between circuit blocks in an integrated circuit, such as macros and standard cells. A macro is wrapped in a relatively narrow power interface ring and placed in the integrated circuit such that the lower metal layers of the power interface ring are aligned and in direct contact with the power rails of a standard cell block. A power grid is formed above the macro and the upper metal layers of the power interface ring are coupled to the power grid. The upper power grid is tied either to an outer power bus or directly to power pins in the surrounding I/O ring. Data signals may be routed in the I/O ring space.

Abstract: An output of a voltage regulator is a core voltage line that runs adjacent to a die attach area on a packaging substrate. An input of the voltage regulator is typically coupled to a power supply which, in one embodiment, is also an I/O voltage line that runs adjacent to the die attach area. In one embodiment, the core voltage line is shaped as a ring encircling the die attach area on the packaging substrate. In another embodiment, the I/O voltage line is also shaped as a ring encircling the die attach area on the packaging substrate. Further, a semiconductor die having at least one I/O Vdd bond pad and at least one core Vdd bond pad can be mounted in the die attach area. The I/O Vdd bond pad and the core Vdd bond pad can be connected, respectively, to the I/O voltage ring and the core voltage ring.