Patents by Inventor Khurram Zafar
Khurram Zafar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11694009Abstract: Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns.Type: GrantFiled: April 5, 2021Date of Patent: July 4, 2023Assignee: Anchor Semiconductor, Inc.Inventors: Chenmin Hu, Khurram Zafar, Ye Chen, Yue Ma, Rong Lv, Justin Chen, Abhishek Vikram, Yuan Xu, Ping Zhang
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Publication number: 20210326505Abstract: Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns.Type: ApplicationFiled: April 5, 2021Publication date: October 21, 2021Inventors: Chenmin Hu, Khurram Zafar, Ye Chen, Yue Ma, Rong Lv, Justin Chen, Abhishek Vikram, Yuan Xu, Ping Zhang
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Patent number: 10997340Abstract: Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns.Type: GrantFiled: November 26, 2019Date of Patent: May 4, 2021Assignee: Anchor Semiconductor Inc.Inventors: Chenmin Hu, Khurram Zafar, Ye Chen, Yue Ma, Rong Lv, Justin Chen, Abhishek Vikram, Yuan Xu, Ping Zhang
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Publication number: 20200097621Abstract: Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns.Type: ApplicationFiled: November 26, 2019Publication date: March 26, 2020Inventors: Chenmin Hu, Khurram Zafar, Ye Chen, Yue Ma, Rong Lv, Justin Chen, Abhishek Vikram, Yuan Xu, Ping Zhang
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Patent number: 10546085Abstract: Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns.Type: GrantFiled: April 3, 2018Date of Patent: January 28, 2020Assignee: Anchor Semiconductor Inc.Inventors: Chenmin Hu, Khurram Zafar, Ye Chen, Yue Ma, Rong Lv, Justin Chen, Abhishek Vikram, Yuan Xu, Ping Zhang
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Publication number: 20180300434Abstract: Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns.Type: ApplicationFiled: April 3, 2018Publication date: October 18, 2018Inventors: Chenmin Hu, Khurram Zafar, Ye Chen, Yue Ma, Rong Lv, Justin Chen, Abhishek Vikram, Yuan Xu, Ping Zhang
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Patent number: 10062160Abstract: Tracking patterns during a semiconductor fabrication process includes: obtaining an image of a portion of a fabricated device; extracting contours of the portion of the fabricated device from the obtained image; aligning the extracted contour to a matching section of a reference design; decomposing the matching section of the reference design into one or more patterns; and updating a pattern tracking database with information pertaining to at least one pattern in the one or more patterns generated as a result of the decomposition.Type: GrantFiled: September 20, 2017Date of Patent: August 28, 2018Assignee: Anchor Semiconductor Inc.Inventors: Khurram Zafar, Chenmin Hu, Ye Chen, Yue Ma, Chingyun Hsiang, Justin Chen, Raymond Xu, Abhishek Vikram, Ping Zhang
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Publication number: 20180033132Abstract: Tracking patterns during a semiconductor fabrication process includes: obtaining an image of a portion of a fabricated device; extracting contours of the portion of the fabricated device from the obtained image; aligning the extracted contour to a matching section of a reference design; decomposing the matching section of the reference design into one or more patterns; and updating a pattern tracking database with information pertaining to at least one pattern in the one or more patterns generated as a result of the decomposition.Type: ApplicationFiled: September 20, 2017Publication date: February 1, 2018Inventors: Khurram Zafar, Chenmin Hu, Ye Chen, Yue Ma, Chingyun Hsiang, Justin Chen, Raymond Xu, Abhishek Vikram, Ping Zhang
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Patent number: 9846934Abstract: Tracking patterns during a semiconductor fabrication process includes: obtaining an image of a portion of a fabricated device; extracting contours of the portion of the fabricated device from the obtained image; aligning the extracted contour to a matching section of a reference design; decomposing the matching section of the reference design into one or more patterns; and updating a pattern tracking database with information pertaining to at least one pattern in the one or more patterns generated as a result of the decomposition.Type: GrantFiled: March 10, 2016Date of Patent: December 19, 2017Assignee: Anchor Semiconductor Inc.Inventors: Khurram Zafar, Chenmin Hu, Ye Chen, Yue Ma, Chingyun Hsiang, Justin Chen, Raymond Xu, Abhishek Vikram, Ping Zhang
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Publication number: 20160300338Abstract: Tracking patterns during a semiconductor fabrication process includes: obtaining an image of a portion of a fabricated device; extracting contours of the portion of the fabricated device from the obtained image; aligning the extracted contour to a matching section of a reference design; decomposing the matching section of the reference design into one or more patterns; and updating a pattern tracking database with information pertaining to at least one pattern in the one or more patterns generated as a result of the decomposition.Type: ApplicationFiled: March 10, 2016Publication date: October 13, 2016Inventors: Khurram Zafar, Chenmin Hu, Ye Chen, Yue Ma, Chingyun Hsiang, Justin Chen, Raymond Xu, Abhishek Vikram, Ping Zhang
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Patent number: 9401014Abstract: Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.Type: GrantFiled: December 19, 2014Date of Patent: July 26, 2016Assignee: KLA-Tencor Technologies Corp.Inventors: Khurram Zafar, Sagar Kekare, Ellis Chang, Allen Park, Peter Rose
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Patent number: 9087367Abstract: Methods and systems for determining design coordinates for defects detected on a wafer are provided. One method includes aligning a design for a wafer to defect review tool images for defects detected in multiple swaths on the wafer by an inspection tool, determining a position of each of the defects in design coordinates based on results of the aligning, separately determining a defect position offset for each of the multiple swaths based on the swath in which each of the defects was detected (swath correction factor), the design coordinates for each of the defects, and a position for each of the defects determined by the inspection tool, and determining design coordinates for the other defects detected in the multiple swaths by the inspection tool by applying the appropriate swath correction factor to those defects.Type: GrantFiled: August 31, 2012Date of Patent: July 21, 2015Assignee: KLA-Tencor Corp.Inventors: Ellis Chang, Michael J. Van Riet, Allen Park, Khurram Zafar, Santosh Bhattacharyya
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Publication number: 20150154746Abstract: Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.Type: ApplicationFiled: December 19, 2014Publication date: June 4, 2015Inventors: Khurram Zafar, Sagar Kekare, Ellis Chang, Allen Park, Peter Rose
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Patent number: 8989479Abstract: The present invention includes searching imagery data in order to identify one or more patterned regions on a semiconductor wafer, generating one or more virtual Fourier filter (VFF) working areas, acquiring an initial set of imagery data from the VFF working areas, defining VFF training blocks within the identified patterned regions of the VFF working areas utilizing the initial set of imagery data, wherein each VFF training block is defined to encompass a portion of the identified patterned region displaying a selected repeating pattern, calculating an initial spectrum for each VFF training block utilizing the initial set of imagery data from the VFF training blocks, and generating a VFF for each training block by identifying frequencies of the initial spectrum having maxima in the frequency domain, wherein the VFF is configured to null the magnitude of the initial spectrum at the frequencies identified to display spectral maxima.Type: GrantFiled: August 1, 2011Date of Patent: March 24, 2015Assignee: KLA-Tencor CorporationInventors: Lisheng Gao, Kenong Wu, Allen Park, Ellis Chang, Khurram Zafar, Junqing Huang, Ping Gu, Christopher Maher, Grace H. Chen, Songnian Rong, Liu-Ming Wu
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Patent number: 8923600Abstract: Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.Type: GrantFiled: August 3, 2009Date of Patent: December 30, 2014Assignee: KLA-Tencor Technologies Corp.Inventors: Khurram Zafar, Sagar Kekare, Ellis Chang, Allen Park, Peter Rose
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Publication number: 20130064442Abstract: Methods and systems for determining design coordinates for defects detected on a wafer are provided. One method includes aligning a design for a wafer to defect review tool images for defects detected in multiple swaths on the wafer by an inspection tool, determining a position of each of the defects in design coordinates based on results of the aligning, separately determining a defect position offset for each of the multiple swaths based on the swath in which each of the defects was detected (swath correction factor), the design coordinates for each of the defects, and a position for each of the defects determined by the inspection tool, and determining design coordinates for the other defects detected in the multiple swaths by the inspection tool by applying the appropriate swath correction factor to those defects.Type: ApplicationFiled: August 31, 2012Publication date: March 14, 2013Applicant: KLA-TENCOR CORPORATIONInventors: Ellis Chang, Michael J. Van Riet, Allen Park, Khurram Zafar, Santosh Bhattacharyya
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Publication number: 20120141013Abstract: The present invention includes searching imagery data in order to identify one or more patterned regions on a semiconductor wafer, generating one or more virtual Fourier filter (VFF) working areas, acquiring an initial set of imagery data from the VFF working areas, defining VFF training blocks within the identified patterned regions of the VFF working areas utilizing the initial set of imagery data, wherein each VFF training block is defined to encompass a portion of the identified patterned region displaying a selected repeating pattern, calculating an initial spectrum for each VFF training block utilizing the initial set of imagery data from the VFF training blocks, and generating a VFF for each training block by identifying frequencies of the initial spectrum having maxima in the frequency domain, wherein the VFF is configured to null the magnitude of the initial spectrum at the frequencies identified to display spectral maxima.Type: ApplicationFiled: August 1, 2011Publication date: June 7, 2012Applicant: KLA-TENCOR CORPORATIONInventors: Lisheng Gao, Kenong Wu, Allen Park, Ellis Chang, Khurram Zafar, Junqing Huang, Ping Gu, Christopher Maher, Grace H. Chen, Songnian Rong, Liu-Ming Wu
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Publication number: 20090297019Abstract: Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.Type: ApplicationFiled: August 3, 2009Publication date: December 3, 2009Applicant: KLA-TENCOR TECHNOLOGIES CORPORATIONInventors: Khurram Zafar, Sagar Kekare, Ellis Chang, Allen Park, Peter Rose
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Patent number: 7570796Abstract: Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.Type: GrantFiled: November 20, 2006Date of Patent: August 4, 2009Assignee: KLA-Tencor Technologies Corp.Inventors: Khurram Zafar, Sagar Kekare, Ellis Chang, Allen Park, Peter Rose
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Publication number: 20070288219Abstract: Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.Type: ApplicationFiled: November 20, 2006Publication date: December 13, 2007Inventors: Khurram Zafar, Sagar Kekare, Ellis Chang, Allen Park, Peter Rose