Abstract: A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip.

Abstract: A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip.

Abstract: A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip.

Abstract: Disclosed herein is a stacked package. The stacked package includes two or more of a first BGA package and a second BGA package and a circuit board having a circuit pattern. The first BGA package is mounted on one face of the circuit board, and the second BGA package is mounted on the other face of the circuit board. A signal connection member is provided for transmitting signals of the first BGA package and the second BGA package to each other. The second BGA package is provided with a signal connection pad. One end of the signal connection member is bonded to the signal connection pad and the other end of the signal connection member is bonded to the circuit pattern of the circuit board. A method of fabricating the stacked package is also disclosed.

Abstract: Disclosed are a stack package and a fabricating method thereof using a ball grid array semiconductor package (hereinafter, referred to as “BGA PKG”). The stack package can easily electrically connect the stacked BGA PKGs with each other by simplifying a stack structure between the BGA PKGs, and increase bonding reliability by improving bonding force bonded portions of solder balls of substrates.

Abstract: Disclosed are a stack package and a method of manufacturing the same, which has improved electrical properties by virtue of a reduced signal line length, and also allows reduction of production costs of the stack package. The stack package of the present invention includes panels having an area for mounting respective CSP packages and pin-shaped connectors. The panels include circuit patterns for electrical connection to the CSP packages, which are formed at portions of the panels corresponding to the CSP packages to be mounted. Also, the panels have first openings for electrical connection to the circuit patterns, which are formed at both sides of the circuit patterns. The pin-shaped connectors are inserted through the first openings of the panels. The panels are stacked in at least two layers in such a manner that the first openings of one panel correspond to the first openings of the other panels, so that the connectors are electrically connected to the circuit patterns of the stacked panels.

Abstract: Disclosed are a stack package and a fabricating method thereof using a ball grid array semiconductor package(hereinafter, referred to as “BGA PKG”). The stack package can easily electrically connect the stacked BGA PKGs with each other by simplifying a stack structure between the BGA PKGs, and increase bonding reliability by improving bonding force bonded portions of solder balls of substrates.

Abstract: Disclosed are a stack package and a method of manufacturing the same, which has improved electrical properties by virtue of a reduced signal line length, and also allows reduction of production costs of the stack package. The stack package of the present invention comprises panels having an area for mounting respective CSP packages and pin-shaped connectors. The panels comprise circuit patterns for electrical connection to the CSP packages, which are formed at portions of the panels corresponding to the CSP packages to be mounted. Also, the panels have first openings for electrical connection to the circuit patterns, which are formed at both sides of the circuit patterns. The pin-shaped connectors are inserted through the first openings of the panels. The panels are stacked in at least two layers in such a manner that the first openings of one panel correspond to the first openings of the other panels, so that the connectors are electrically connected to the circuit patterns of the stacked panels.

Abstract: A chip-size semiconductor package and fabrication method is provided that reduces the size of the package. Further, the electrical path from the chip pads to the external leads is reduced to improve electrical characteristics. In addition, the external leads can be formed directly at the location of the chip pads. The chip-size semiconductor package has a passivation film is formed on a semiconductor chip excluding the chip pads thereon. Inner ends of conductive wires are vertically coupled to corresponding chip pads, respectively. Then, the semiconductor chip is sealed with a molding resin excluding the outer ends of the conductive wires that protrude. The outer ends can be formed as external leads having a shape, such as circular external balls, based on the intended use.