Patents by Inventor Ki-Heung Kim
Ki-Heung Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11921579Abstract: A method of operating a memory device is provided. The method includes: receiving a first command from a controller; activating a page of a memory cell array based on the first command; reading data of the activated page; detecting an error from the read data; correcting the detected error to generate error correction data; writing back the error correction data to the activated page in based on the detected error being a single-bit error; and blocking write-back of the error correction data to the activated page based on the detected error being a multi-bit error.Type: GrantFiled: March 11, 2022Date of Patent: March 5, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki-Heung Kim, Jun Hyung Kim, Chang-Yong Lee, Sang Uhn Cha, Kyung-Soo Ha
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Patent number: 11681457Abstract: According to some embodiments, for a memory device including a base die and a stack of memory dies including a plurality of memory dies stacked on the base die, the base die including a plurality of first input/output (i/o) terminals that are command/address and data terminals and a plurality of second i/o terminals that are direct access terminals, a method includes receiving at the plurality of first i/o terminals a command/address, a clock signal, and data; first transmitting the command/address, clock signal, and data received by the plurality of first i/o terminals from the base die to the stack of memory dies; and second transmitting at least part of one or more of the command/address, clock signal, and data received by a set of the plurality of first i/o terminals through a circuit of the base die to the plurality of second i/o terminals.Type: GrantFiled: April 25, 2022Date of Patent: June 20, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun Gyu Lee, Reum Oh, Ki Heung Kim, Moon Hee Oh
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Publication number: 20230012525Abstract: A method of operating a memory device is provided. The method includes: receiving a first command from a controller; activating a page of a memory cell array based on the first command; reading data of the activated page; detecting an error from the read data; correcting the detected error to generate error correction data; writing back the error correction data to the activated page in based on the detected error being a single-bit error; and blocking write-back of the error correction data to the activated page based on the detected error being a multi-bit error.Type: ApplicationFiled: March 11, 2022Publication date: January 19, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ki-Heung KIM, Jun Hyung KIM, Chang-Yong LEE, Sang Uhn CHA, Kyung-Soo HA
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Publication number: 20220244882Abstract: According to some embodiments, for a memory device including a base die and a stack of memory dies including a plurality of memory dies stacked on the base die, the base die including a plurality of first input/output (i/o) terminals that are command/address and data terminals and a plurality of second i/o terminals that are direct access terminals, a method includes receiving at the plurality of first i/o terminals a command/address, a clock signal, and data; first transmitting the command/address, clock signal, and data received by the plurality of first i/o terminals from the base die to the stack of memory dies; and second transmitting at least part of one or more of the command/address, clock signal, and data received by a set of the plurality of first i/o terminals through a circuit of the base die to the plurality of second i/o terminals.Type: ApplicationFiled: April 25, 2022Publication date: August 4, 2022Inventors: JUN GYU LEE, REUM OH, KI HEUNG KIM, MOON HEE OH
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Patent number: 11334282Abstract: According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of through substrate vias. The base die includes a plurality of first input buffers configured to receive channel clock signals, channel command/addresses, and channel data from a plurality of first bumps connected to the outside of the base die, a plurality of second input buffers configured to receive test clock signals, test command/addresses, and test data from a plurality of second bumps connected to the outside of the base die, a monitoring unit, a plurality of first output buffers connected to the monitoring unit and configured to output monitored data from the monitoring unit to the plurality of second bumps, and a plurality of paths from the plurality of first input buffers to the monitoring unit.Type: GrantFiled: February 11, 2021Date of Patent: May 17, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun Gyu Lee, Reum Oh, Ki Heung Kim, Moon Hee Oh
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Patent number: 11194505Abstract: According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of through substrate vias. The base die includes a plurality of first input buffers configured to receive channel clock signals, channel command/addresses, and channel data from a plurality of first bumps connected to the outside of the base die, a plurality of second input buffers configured to receive test clock signals, test command/addresses, and test data from a plurality of second bumps connected to the outside of the base die, a monitoring unit, a plurality of first output buffers connected to the monitoring unit and configured to output monitored data from the monitoring unit to the plurality of second bumps, and a plurality of paths from the plurality of first input buffers to the monitoring unit.Type: GrantFiled: February 11, 2021Date of Patent: December 7, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun Gyu Lee, Reum Oh, Ki Heung Kim, Moon Hee Oh
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Patent number: 11049584Abstract: An integrated circuit device includes a stack of integrated circuit memory dies having a plurality of through-substrate vias (TSVs) extending therethrough, and a buffer die electrically coupled to the plurality of TSVs. The buffer die includes a test interface circuit, which is configured to: (i) generate a plurality of internal test signals, which are synchronized with a second clock signal having a second frequency, from at least one control code, and from a plurality of external test signals, which are synchronized with a first clock signal having a first frequency less than the second frequency, and (ii) provide the plurality of internal test signals to at least one of the memory dies in said stack during a first test mode. The second frequency may be greater than three (3) times the first frequency.Type: GrantFiled: September 18, 2019Date of Patent: June 29, 2021Inventors: Ki-Heung Kim, Kyo-Min Sohn, Young-Soo Sohn
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Publication number: 20210165597Abstract: According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of through substrate vias. The base die includes a plurality of first input buffers configured to receive channel clock signals, channel command/addresses, and channel data from a plurality of first bumps connected to the outside of the base die, a plurality of second input buffers configured to receive test clock signals, test command/addresses, and test data from a plurality of second bumps connected to the outside of the base die, a monitoring unit, a plurality of first output buffers connected to the monitoring unit and configured to output monitored data from the monitoring unit to the plurality of second bumps, and a plurality of paths from the plurality of first input buffers to the monitoring unit.Type: ApplicationFiled: February 11, 2021Publication date: June 3, 2021Inventors: JUN GYU LEE, REUM OH, KI HEUNG KIM, MOON HEE OH
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Publication number: 20210165596Abstract: According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of through substrate vias. The base die includes a plurality of first input buffers configured to receive channel clock signals, channel command/addresses, and channel data from a plurality of first bumps connected to the outside of the base die, a plurality of second input buffers configured to receive test clock signals, test command/addresses, and test data from a plurality of second bumps connected to the outside of the base die, a monitoring unit, a plurality of first output buffers connected to the monitoring unit and configured to output monitored data from the monitoring unit to the plurality of second bumps, and a plurality of paths from the plurality of first input buffers to the monitoring unit.Type: ApplicationFiled: February 11, 2021Publication date: June 3, 2021Inventors: JUN GYU LEE, REUM OH, KI HEUNG KIM, MOON HEE OH
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Patent number: 10996885Abstract: According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of through substrate vias. The base die includes a plurality of first input buffers configured to receive channel clock signals, channel command/addresses, and channel data from a plurality of first bumps connected to the outside of the base die, a plurality of second input buffers configured to receive test clock signals, test command/addresses, and test data from a plurality of second bumps connected to the outside of the base die, a monitoring unit, a plurality of first output buffers connected to the monitoring unit and configured to output monitored data from the monitoring unit to the plurality of second bumps, and a plurality of paths from the plurality of first input buffers to the monitoring unit.Type: GrantFiled: December 4, 2018Date of Patent: May 4, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun Gyu Lee, Reum Oh, Ki Heung Kim, Moon Hee Oh
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Publication number: 20200227130Abstract: An integrated circuit device includes a stack of integrated circuit memory dies having a plurality of through-substrate vias (TSVs) extending therethrough, and a buffer die electrically coupled to the plurality of TSVs. The buffer die includes a test interface circuit, which is configured to: (i) generate a plurality of internal test signals, which are synchronized with a second clock signal having a second frequency, from at least one control code, and from a plurality of external test signals, which are synchronized with a first clock signal having a first frequency less than the second frequency, and (ii) provide the plurality of internal test signals to at least one of the memory dies in said stack during a first test mode. The second frequency may be greater than three (3) times the first frequency.Type: ApplicationFiled: September 18, 2019Publication date: July 16, 2020Inventors: Ki-Heung Kim, Kyo-Min Sohn, Young-Soo Sohn
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Publication number: 20190278511Abstract: According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of through substrate vias. The base die includes a plurality of first input buffers configured to receive channel clock signals, channel command/addresses, and channel data from a plurality of first bumps connected to the outside of the base die, a plurality of second input buffers configured to receive test clock signals, test command/addresses, and test data from a plurality of second bumps connected to the outside of the base die, a monitoring unit, a plurality of first output buffers connected to the monitoring unit and configured to output monitored data from the monitoring unit to the plurality of second bumps, and a plurality of paths from the plurality of first input buffers to the monitoring unit.Type: ApplicationFiled: December 4, 2018Publication date: September 12, 2019Inventors: JUN GYU LEE, REUM OH, KI HEUNG KIM, MOON HEE OH
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Patent number: 8902686Abstract: A method of repairing a word line of a memory device includes receiving a row address, comparing a received row address with a row address of a defective cell, enabling a normal word line and a redundant word line, which correspond to the row address, according to a result of the row address comparison, receiving a column address, comparing a received column address with a column address of the defective cell, and performing a memory access operation on one of the normal word line and the redundant word line according to a result of the column address comparison.Type: GrantFiled: March 15, 2013Date of Patent: December 2, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: In Chul Jeong, Ki Heung Kim
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Patent number: 8837246Abstract: A memory refresh method includes selecting at least one bank from among N banks of a memory device, and activating K word lines from among a plurality of word lines included in the at least one bank during one of L refresh cycles of a refresh period. Each of the N banks comprises M word lines, N, K and M are each a natural number greater than or equal to two, L is a natural number less than or equal to M, and K is equal to M*N/L.Type: GrantFiled: March 14, 2013Date of Patent: September 16, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ki Heung Kim, In Chul Jeong
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Publication number: 20130336079Abstract: A memory refresh method includes selecting at least one bank from among N banks of a memory device, and activating K word lines from among a plurality of word lines included in the at least one bank during one of L refresh cycles of a refresh period. Each of the N banks comprises M word lines, N, K and M are each a natural number greater than or equal to two, L is a natural number less than or equal to M, and K is equal to M*N/L.Type: ApplicationFiled: March 14, 2013Publication date: December 19, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: KI HEUNG KIM, In Chul Jeong
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Publication number: 20130336076Abstract: A method of repairing a word line of a memory device includes receiving a row address, comparing a received row address with a row address of a defective cell, enabling a normal word line and a redundant word line, which correspond to the row address, according to a result of the row address comparison, receiving a column address, comparing a received column address with a column address of the defective cell, and performing a memory access operation on one of the normal word line and the redundant word line according to a result of the column address comparison.Type: ApplicationFiled: March 15, 2013Publication date: December 19, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: In Chul JEONG, Ki Heung KIM
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Patent number: 8483001Abstract: A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and an internal voltage driver that adjusts an external supply voltage in response to the comparative voltage and that outputs an internal voltage.Type: GrantFiled: September 12, 2012Date of Patent: July 9, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-Heung Kim, Yong-Ho Cho, Ji-Hoon Lim, Seong-Jin Jang, Tae-Yoon Lee
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Patent number: 8416632Abstract: A bitline precharge voltage generator comprises a leakage trimming unit and a bitline precharge voltage providing unit. The leakage trimming unit applies a leakage current to an output node to place a bitline precharge voltage at an edge of a dead zone. The bitline precharge voltage providing unit provides the bitline precharge voltage to the output node, and sets the bitline precharge voltage to a target level. The bitline precharge voltage generator generates the bitline precharge voltage having a distribution including the dead zone.Type: GrantFiled: October 14, 2010Date of Patent: April 9, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-Heung Kim, Seong-Jin Jang, Myeong-O Kim, Hong-Jun Lee, Tae-Yoon Lee
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Publication number: 20130002217Abstract: A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and an internal voltage driver that adjusts an external supply voltage in response to the comparative voltage and that outputs an internal voltage.Type: ApplicationFiled: September 12, 2012Publication date: January 3, 2013Inventors: KI-HEUNG KIM, YONG-HO CHO, JI-HOON LIM, SEONG-JIN JANG, TAE-YOON LEE
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Patent number: 8284624Abstract: A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and an internal voltage driver that adjusts an external supply voltage in response to the comparative voltage and that outputs an internal voltage.Type: GrantFiled: January 22, 2010Date of Patent: October 9, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Ki-Heung Kim, Yong-Ho Cho, Ji-Hoon Lim, Seong-Jin Jang, Tae-Yoon Lee