Patents by Inventor Ki-Hyung Lee

Ki-Hyung Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacturing a semiconductor device having a one time programmable (OTP) erasable and programmable read only memory (EPROM) cell
    Patent number: 7491657
    Abstract: Provided is an erasable and programmable read only memory (EPROM) device in which a plasma enhanced oxide (PEOX) film covers an upper surface of a floating gate in a single poly one time programmable (OTP) cell and a method of manufacturing a semiconductor device having the same. The semiconductor device comprises a substrate having an OTP cell region, on which a floating gate is formed for making an OTP cell transistor, and a main chip region, on which a gate of a transistor is formed. A PEOX film is formed on the OTP cell region and the main chip region. The PEOX film covers the floating gate in a close state and covers the gate by a predetermined distance. A silicon oxy nitride (SiON) film Is interposed between the gate and the PEOX film in the main chip region.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: February 17, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Hyung Lee, Seung-Han Yoo
  • ERASABLE AND PROGRAMMABLE READ ONLY MEMORY (EPROM) CELL OF AN EPROM DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING THE EPROM CELL
    Publication number: 20070148871
    Abstract: Provided is an erasable and programmable read only memory (EPROM) device in which a plasma enhanced oxide (PEOX) film covers an upper surface of a floating gate in a single poly one time programmable (OTP) cell and a method of manufacturing a semiconductor device having the same. The semiconductor device comprises a substrate having an OTP cell region, on which a floating gate is formed for making an OTP cell transistor, and a main chip region, on which a gate of a transistor is formed. A PEOX film is formed on the OTP cell region and the main chip region. The PEOX film covers the floating gate in a close state and covers the gate by a predetermined distance. A silicon oxy nitride (SiON) film Is interposed between the gate and the PEOX film in the main chip region.
    Type: Application
    Filed: March 2, 2007
    Publication date: June 28, 2007
    Inventors: Ki-Hyung Lee, Seung-Han Yoo
  • Erasable and programmable read only memory (EPROM) cell of an EPROM device and method of manufacturing a semiconductor device having the EPROM cell
    Patent number: 7202522
    Abstract: Provided is an erasable and programmable read only memory (EPROM) device in which a plasma enhanced oxide (PEOX) film covers an upper surface of a floating gate in a single poly one time programmable (OTP) cell and a method of manufacturing a semiconductor device having the same. The semiconductor device comprises a substrate having an OTP cell region, on which a floating gate is formed for making an OTP cell transistor, and a main chip region, on which a gate of a transistor is formed. A PEOX film is formed on the OTP cell region and the main chip region. The PEOX film covers the floating gate in a close state and covers the gate by a predetermined distance. A silicon oxy nitride (SiON) film is interposed between the gate and the PEOX film in the main chip region.
    Type: Grant
    Filed: October 26, 2004
    Date of Patent: April 10, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki-Hyung Lee, Seung-Han Yoo
  • Erasable and programmable read only memory (EPROM) device and method of manufacturing a semiconductor device having the same
    Publication number: 20050093079
    Abstract: Provided is an erasable and programmable read only memory (EPROM) device in which a plasma enhanced oxide (PEOX) film covers an upper surface of a floating gate in a single poly one time programmable (OTP) cell and a method of manufacturing a semiconductor device having the same. The semiconductor device comprises a substrate having an OTP cell region, on which a floating gate is formed for making an OTP cell transistor, and a main chip region, on which a gate of a transistor is formed. A PEOX film is formed on the OTP cell region and the main chip region. The PEOX film covers the floating gate in a close state and covers the gate by a predetermined distance. A silicon oxy nitride (SiON) film is interposed between the gate and the PEOX film in the main chip region.
    Type: Application
    Filed: October 26, 2004
    Publication date: May 5, 2005
    Inventors: Ki-Hyung Lee, Seung-Han Yoo